Texas Instruments

Table of Contents

IAR Cortex-M3 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC2650:1

Tool Chain Version: 7.80.1.28

BIOS Version: bios_6_50_00_06_eng

XDCTools Version: xdctools_3_50_00_09_eng

Benchmark Cycles
Interrupt Latency 168
Hwi_restore() 14
Hwi_disable() 15
Hwi dispatcher prolog 120
Hwi dispatcher epilog 205
Hwi dispatcher 314
Hardware Interrupt to Blocked Task 538
Hardware Interrupt to Software Interrupt 387
Swi_enable() 76
Swi_disable() 17
Post Software Interrupt Again 36
Post Software Interrupt without Context Switch 101
Post Software Interrupt with Context Switch 212
Create a New Task without Context Switch 4636
Set a Task Priority without a Context Switch 190
Task_yield() 212
Post Semaphore No Waiting Task 59
Post Semaphore No Task Switch 201
Post Semaphore with Task Switch 265
Pend on Semaphore No Context Switch 70
Pend on Semaphore with Task Switch 299
Clock_getTicks() 312
POSIX Create a New Task without Context Switch 7354
POSIX Set a Task Priority without a Context Switch 269
POSIX Post Semaphore No Waiting Task 72
POSIX Post Semaphore No Task Switch 214
POSIX Post Semaphore with Task Switch 278
POSIX Pend on Semaphore No Context Switch 84
POSIX Pend on Semaphore with Task Switch 313

The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.