Texas Instruments

Table of Contents

IAR Cortex-M3 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC1350:1

Tool Chain Version: 7.80.1.28

BIOS Version: bios_6_50_00_06_eng

XDCTools Version: xdctools_3_50_00_09_eng

Benchmark Cycles
Interrupt Latency 173
Hwi_restore() 15
Hwi_disable() 16
Hwi dispatcher prolog 121
Hwi dispatcher epilog 205
Hwi dispatcher 315
Hardware Interrupt to Blocked Task 540
Hardware Interrupt to Software Interrupt 389
Swi_enable() 75
Swi_disable() 18
Post Software Interrupt Again 37
Post Software Interrupt without Context Switch 102
Post Software Interrupt with Context Switch 213
Create a New Task without Context Switch 4637
Set a Task Priority without a Context Switch 188
Task_yield() 213
Post Semaphore No Waiting Task 60
Post Semaphore No Task Switch 202
Post Semaphore with Task Switch 266
Pend on Semaphore No Context Switch 71
Pend on Semaphore with Task Switch 300
Clock_getTicks() 312
POSIX Create a New Task without Context Switch 7355
POSIX Set a Task Priority without a Context Switch 265
POSIX Post Semaphore No Waiting Task 73
POSIX Post Semaphore No Task Switch 215
POSIX Post Semaphore with Task Switch 279
POSIX Pend on Semaphore No Context Switch 85
POSIX Pend on Semaphore with Task Switch 314

The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.