Texas Instruments

Table of Contents

GCC Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 4.9.3

BIOS Version: bios_6_50_00_06_eng

XDCTools Version: xdctools_3_50_00_09_eng

Benchmark Cycles
Interrupt Latency 152
Hwi_restore() 7
Hwi_disable() 9
Hwi dispatcher prolog 139
Hwi dispatcher epilog 234
Hwi dispatcher 364
Hardware Interrupt to Blocked Task 673
Hardware Interrupt to Software Interrupt 390
Swi_enable() 65
Swi_disable() 13
Post Software Interrupt Again 29
Post Software Interrupt without Context Switch 77
Post Software Interrupt with Context Switch 183
Create a New Task without Context Switch 1971
Set a Task Priority without a Context Switch 156
Task_yield() 290
Post Semaphore No Waiting Task 50
Post Semaphore No Task Switch 247
Post Semaphore with Task Switch 388
Pend on Semaphore No Context Switch 60
Pend on Semaphore with Task Switch 400
Clock_getTicks() 8
POSIX Create a New Task without Context Switch 3432
POSIX Set a Task Priority without a Context Switch 230
POSIX Post Semaphore No Waiting Task 61
POSIX Post Semaphore No Task Switch 261
POSIX Post Semaphore with Task Switch 401
POSIX Pend on Semaphore No Context Switch 71
POSIX Pend on Semaphore with Task Switch 413

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:

“-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.