interface ti.sysbios.interfaces.ICache

Cache Interface

XDCspec summary sourced in ti/sysbios/interfaces/ICache.xdc
interface ICache {  ...
// inherits xdc.runtime.IModule
XDCspec declarations sourced in ti/sysbios/interfaces/ICache.xdc
 
interface ICache {
module-wide constants & types
        Type_L1// Level 1 caches,
        Type_L2// Level 2 caches,
        Type_ALLD// All Data caches,
        Type_ALL// All caches
    };
module-wide config parameters
module-wide functions
    Void disable// Disables the 'type' cache(s)(Bits16 type);
    Void enable// Enables all cache(s)(Bits16 type);
    Void wb// Writes back a range of memory from all cache(s)(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
}
 
enum ICache.Type

Lists of bitmask cache types

XDCspec declarations sourced in ti/sysbios/interfaces/ICache.xdc
enum Type {
    Type_L1P,
    // Level 1 Program cache
    Type_L1D,
    // Level 1 Data cache
    Type_L1,
    // Level 1 caches
    Type_L2P,
    // Level 2 Program cache
    Type_L2D,
    // Level 2 Data cache
    Type_L2,
    // Level 2 caches
    Type_ALLP,
    // All Program caches
    Type_ALLD,
    // All Data caches
    Type_ALL
    // All caches
};
 
 
metaonly config ICache.common$  // module-wide

Common module configuration parameters

XDCspec declarations sourced in ti/sysbios/interfaces/ICache.xdc
metaonly config Types.Common$ common$;
 
DETAILS
All modules have this configuration parameter. Its name contains the '$' character to ensure it does not conflict with configuration parameters declared by the module. This allows new configuration parameters to be added in the future without any chance of breaking existing modules.
 
ICache.disable()  // module-wide

Disables the 'type' cache(s)

XDCspec declarations sourced in ti/sysbios/interfaces/ICache.xdc
Void disable(Bits16 type);
 
ARGUMENTS
type — bit mask of Cache type
 
ICache.enable()  // module-wide

Enables all cache(s)

XDCspec declarations sourced in ti/sysbios/interfaces/ICache.xdc
Void enable(Bits16 type);
 
ARGUMENTS
type — bit mask of Cache type
 
ICache.inv()  // module-wide

Invalidate the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines in range are invalidated for all the 'type' caches

XDCspec declarations sourced in ti/sysbios/interfaces/ICache.xdc
Void inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
 
ICache.wait()  // module-wide

Wait for a previous cache operation to complete

XDCspec declarations sourced in ti/sysbios/interfaces/ICache.xdc
Void wait();
 
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache operation is not truly complete until it has worked its way through all buffering and all memory writes have landed in the source memory.
 
ICache.wb()  // module-wide

Writes back a range of memory from all cache(s)

XDCspec declarations sourced in ti/sysbios/interfaces/ICache.xdc
Void wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
DETAILS
Writes back the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are left valid in the 'type' caches and the data within the range will be written back to the source memory.
 
ICache.wbAll()  // module-wide

Write back all caches

XDCspec declarations sourced in ti/sysbios/interfaces/ICache.xdc
Void wbAll();
 
DETAILS
Perform a global write back. There is no effect on program cache. All data cache lines are left valid.
 
ICache.wbInv()  // module-wide

Writes back and invalidates the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are written back to the source memory and then invalidated for all 'type' caches

XDCspec declarations sourced in ti/sysbios/interfaces/ICache.xdc
Void wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
 
ICache.wbInvAll()  // module-wide

Write back invalidate all caches

XDCspec declarations sourced in ti/sysbios/interfaces/ICache.xdc
Void wbInvAll();
 
DETAILS
Performs a global write back and invalidate. All cache lines are written out to physical memory and then invalidated.
generated on Tue, 14 Feb 2017 19:59:34 GMT