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32 33 34
35
36 package ti.sysbios.hal.ammu;
37
38 import xdc.rov.ViewInfo;
39
40 /*!
41 * ======== AMMU ========
42 * Attribute MMU configuration module
43 *
44 * Responsible for initializing the Attribute MMU
45 *
46 * @a(Restrictions)
47 * When used within a dual M3 core (Ducati) arrangement, care must be
48 * taken when initializing this shared resource.
49 * The "Shared Resources" note provided
50 * in the {@link ti.sysbios.family.arm.ducati ducati} package discusses
51 * the management of the various hardware and software resources
52 * shared by the two M3 cores.
53 *
54 * As the AMMU is shared between the two M3 cores, it should only
55 * be initialized and enabled once.
56 * It is intended that Core 0 will {@link #configureAmmu configure}
57 * the AMMU at startup.
58 * @a
59 */
60
61 @DirectCall
62 module AMMU
63 {
64
65
66 /*! @_nodoc */
67 metaonly readonly config xdc.runtime.Types.ViewInfo filteredNameMap$[string] = [
68 ["Filtered Variables", {viewType: "module", viewFxn: "pageSizeFilter",
69 fields: [
70 "largePages", "mediumPages", "smallPages"
71 ]}],
72 ];
73
74 /*! @_nodoc */
75 metaonly any pageSizeFilter(int op, string paramName, string value);
76
77
78
79 /*! @_nodoc */
80 metaonly struct PageView {
81 String Page;
82 Ptr AddrVirtual;
83 String AddrPhysical;
84 Bool Enabled;
85 Bool L1Cacheable;
86 String L1WrPolicy;
87 String L1AllocPolicy;
88 Bool L1Posted;
89 Bool L2Cacheable;
90 String L2WrPolicy;
91 String L2AllocPolicy;
92 Bool L2Posted;
93 Bool ReadOnly;
94 Bool ExecOnly;
95 };
96
97 /*! @_nodoc */
98 @Facet
99 metaonly config ViewInfo.Instance rovViewInfo =
100 ViewInfo.create({
101 viewMap: [
102 ['PageView', {type: ViewInfo.MODULE_DATA,
103 viewInitFxn: 'viewPages',
104 structName: 'PageView'}]
105 ]
106 });
107
108 109 110
111
112 metaonly enum Small {
113 Small_4K,
114 Small_8K,
115 Small_16K,
116 Small_32K
117 };
118
119 metaonly enum Medium {
120 Medium_128K,
121 Medium_256K,
122 Medium_512K,
123 Medium_1M
124 };
125
126 metaonly enum Large {
127 Large_2M,
128 Large_4M,
129 Large_8M,
130 Large_16M,
131 Large_32M,
132 Large_64M,
133 Large_128M,
134 Large_256M,
135 Large_512M
136 };
137
138 metaonly enum Volatile {
139 Volatile_DO_NOT_FOLLOW,
140 Volatile_FOLLOW
141 };
142
143 metaonly enum CachePolicy {
144 CachePolicy_NON_CACHEABLE,
145 CachePolicy_CACHEABLE
146 };
147
148 metaonly enum PostedPolicy {
149 PostedPolicy_NON_POSTED,
150 PostedPolicy_POSTED
151 };
152
153 metaonly enum AllocatePolicy {
154 AllocatePolicy_NON_ALLOCATE,
155 AllocatePolicy_ALLOCATE
156 };
157
158 metaonly enum WritePolicy {
159 WritePolicy_WRITE_THROUGH,
160 WritePolicy_WRITE_BACK
161 };
162
163 metaonly enum Enable {
164 Enable_NO,
165 Enable_YES
166 };
167
168 169 170
171
172 metaonly struct LargePage {
173 Enable pageEnabled;
174 Ptr logicalAddress;
175
176 Enable translationEnabled;
177 Ptr translatedAddress;
178
179 Large size;
180 Volatile volatileQualifier;
181 Enable executeOnly;
182 Enable readOnly;
183 Enable prefetch;
184 Enable exclusion;
185 CachePolicy L1_cacheable;
186 PostedPolicy L1_posted;
187 AllocatePolicy L1_allocate;
188 WritePolicy L1_writePolicy;
189 CachePolicy L2_cacheable;
190 PostedPolicy L2_posted;
191 AllocatePolicy L2_allocate;
192 WritePolicy L2_writePolicy;
193 };
194
195 metaonly struct MediumPage {
196 Enable pageEnabled;
197 Ptr logicalAddress;
198
199 Enable translationEnabled;
200 Ptr translatedAddress;
201
202 Medium size;
203 Volatile volatileQualifier;
204 Enable executeOnly;
205 Enable readOnly;
206 Enable prefetch;
207 Enable exclusion;
208 CachePolicy L1_cacheable;
209 PostedPolicy L1_posted;
210 AllocatePolicy L1_allocate;
211 WritePolicy L1_writePolicy;
212 CachePolicy L2_cacheable;
213 PostedPolicy L2_posted;
214 AllocatePolicy L2_allocate;
215 WritePolicy L2_writePolicy;
216 };
217
218 metaonly struct SmallPage {
219 Enable pageEnabled;
220 Ptr logicalAddress;
221
222 Enable translationEnabled;
223 Ptr translatedAddress;
224
225 Small size;
226 Volatile volatileQualifier;
227 Enable executeOnly;
228 Enable readOnly;
229 Enable prefetch;
230 Enable exclusion;
231 CachePolicy L1_cacheable;
232 PostedPolicy L1_posted;
233 AllocatePolicy L1_allocate;
234 WritePolicy L1_writePolicy;
235 CachePolicy L2_cacheable;
236 PostedPolicy L2_posted;
237 AllocatePolicy L2_allocate;
238 WritePolicy L2_writePolicy;
239 }
240
241 metaonly enum Maintenance {
242 DO_NOT_PERFORM,
243 PERFORM
244 };
245
246 metaonly enum Invalidate {
247 DO_NOT_INVALIDATE,
248 INVALIDATE
249 };
250
251 metaonly enum Unlock {
252 DO_NOT_UNLOCK,
253 UNLOCK
254 };
255
256 metaonly enum Lock {
257 DO_NOT_LOCK,
258 LOCK
259 };
260
261 metaonly enum Clean {
262 DO_NOT_CLEAN,
263 CLEAN
264 };
265
266 metaonly struct SmallPageMaintenance {
267 Maintenance maintL2Cache;
268 Maintenance maintL1Cache2;
269 Maintenance maintL1Cache1;
270 Enable cpuInterrupt;
271 Enable hostInterrupt;
272 Invalidate invalidate;
273 Clean clean;
274 Unlock unlock;
275 Lock lock;
276 Enable preload;
277 };
278
279 metaonly struct LinePage {
280 Enable pageEnabled;
281 Ptr logicalAddress;
282
283 Enable translationEnabled;
284 Ptr translatedAddress;
285 };
286
287 metaonly struct DebugPage {
288 Enable pageEnabled;
289 Enable translationEnabled;
290 Ptr translatedAddress;
291 };
292
293 /*! The number of Large Page Desciptors is target/device specific */
294 metaonly config LargePage largePages[] = [];
295
296 /*! The number of Medium Page Desciptors is target/device specific */
297 metaonly config MediumPage mediumPages[] = [];
298
299 /*! The number of Small Page Desciptors is target/device specific */
300 metaonly config SmallPage smallPages[] = [];
301
302 /*! The number of Line Page Desciptors is target/device specific */
303 metaonly config LinePage linePages[] = [];
304
305 metaonly config DebugPage debugPage;
306
307 308 309
310 struct MMU {
311 Char *LARGE_ADDR[8];
312 Char *LARGE_XLTE[8];
313 UInt32 LARGE_POLICY[8];
314
315 Char *MEDIUM_ADDR[16];
316 Char *MEDIUM_XLTE[16];
317 UInt32 MEDIUM_POLICY[16];
318
319 Char *SMALL_ADDR[32];
320 Char *SMALL_XLTE[32];
321 UInt32 SMALL_POLICY[32];
322 UInt32 SMALL_MAINT[32];
323
324 Char *LINE_ADDR[32];
325 Char *LINE_XLTE[32];
326 UInt32 LINE_POLICY[32];
327
328 Char *DEBUG_XLTE;
329 UInt32 DEBUG_POLICY;
330
331 UInt32 MAINT;
332 Char *MSTART;
333 Char *MEND;
334 UInt32 MSTAT;
335 };
336
337 /*!
338 * This device's AMMU register set address.
339 * Initialized internally according to build target/device.
340 */
341 extern volatile MMU mmu;
342
343 /*!
344 * By default the AMMU module will configure the AMMU at startup.
345 *
346 * By setting this flag to false (ie for Ducati core1), the AMMU
347 * module APIs are available but the initialization step is suppressed.
348 */
349 config Bool configureAmmu = true;
350
351 /*!
352 * ======== invAll ========
353 * Invalidate entire L1 and L2 caches
354 * Waits for completion.
355 */
356 Void invAll();
357
358 /*!
359 * @_nodoc
360 * ======== dumpAmmu ========
361 * formatted dump of the contents of the AMMU registers
362 */
363 Void dumpAmmu();
364
365 /*!
366 * @_nodoc
367 * ======== init ========
368 * MMU initialization function called at startup
369 */
370 Void init();
371
372 internal:
373
374 config UInt numLargePages;
375 config UInt numMediumPages;
376 config UInt numSmallPages;
377 config UInt numLinePages;
378
379
380 metaonly config Ptr baseAddr;
381
382
383 config MMU mmuInitConfig;
384
385
386 metaonly config String largePageSizeStrings[];
387 metaonly config String mediumPageSizeStrings[];
388 metaonly config String smallPageSizeStrings[];
389 }