module ti.sysbios.hal.CacheNull
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Null Cache module

C synopsis target-domain sourced in ti/sysbios/hal/CacheNull.xdc
#include <ti/sysbios/hal/CacheNull.h>
Functions common to all ICache modules
Void 
CacheNull_disable// Disables the 'type' cache(s)(Bits16 type);
Void 
CacheNull_enable// Enables all cache(s)(Bits16 type);
Void 
CacheNull_inv// Invalidate the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines in range are invalidated for all the 'type' caches(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
Void 
CacheNull_wait// Wait for a previous cache operation to complete();
Void 
CacheNull_wb// Writes back a range of memory from all cache(s)(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
Void 
CacheNull_wbAll// Write back all caches();
Void 
CacheNull_wbInv// Writes back and invalidates the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are written back to the source memory and then invalidated for all 'type' caches(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
Void 
CacheNull_wbInvAll// Write back invalidate all caches();
Functions common to all target modules
CacheNull_Module_getMask// Returns the diagnostics mask for this module, CacheNull_Module_hasMask// Test whether this module has a diagnostics mask, CacheNull_Module_heap// The heap from which this module allocates memory, CacheNull_Module_id// Get this module's unique id, CacheNull_Module_setMask// Set the diagnostics mask for this module, CacheNull_Module_startupDone// Test if this module has completed startup
Typedefs
typedef enum
CacheNull_Type// Lists of bitmask cache types ...
 
 
enum CacheNull_Type
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Lists of bitmask cache types

C synopsis target-domain
typedef enum CacheNull_Type {
    CacheNull_Type_L1P,
    // Level 1 Program cache
    CacheNull_Type_L1D,
    // Level 1 Data cache
    CacheNull_Type_L1,
    // Level 1 caches
    CacheNull_Type_L2P,
    // Level 2 Program cache
    CacheNull_Type_L2D,
    // Level 2 Data cache
    CacheNull_Type_L2,
    // Level 2 caches
    CacheNull_Type_ALLP,
    // All Program caches
    CacheNull_Type_ALLD,
    // All Data caches
    CacheNull_Type_ALL
    // All caches
} CacheNull_Type;
 
 
CacheNull_disable()  // module-wide
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Disables the 'type' cache(s)

C synopsis target-domain
Void CacheNull_disable(Bits16 type);
 
ARGUMENTS
type — bit mask of Cache type
 
CacheNull_enable()  // module-wide
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Enables all cache(s)

C synopsis target-domain
Void CacheNull_enable(Bits16 type);
 
ARGUMENTS
type — bit mask of Cache type
 
CacheNull_inv()  // module-wide
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Invalidate the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines in range are invalidated for all the 'type' caches

C synopsis target-domain
Void CacheNull_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
 
CacheNull_wait()  // module-wide
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Wait for a previous cache operation to complete

C synopsis target-domain
Void CacheNull_wait();
 
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache operation is not truly complete until it has worked its way through all buffering and all memory writes have landed in the source memory.
 
CacheNull_wb()  // module-wide
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Writes back a range of memory from all cache(s)

C synopsis target-domain
Void CacheNull_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
DETAILS
Writes back the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are left valid in the 'type' caches and the data within the range will be written back to the source memory.
 
CacheNull_wbAll()  // module-wide
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Write back all caches

C synopsis target-domain
Void CacheNull_wbAll();
 
DETAILS
Perform a global write back. There is no effect on program cache. All data cache lines are left valid.
 
CacheNull_wbInv()  // module-wide
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Writes back and invalidates the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are written back to the source memory and then invalidated for all 'type' caches

C synopsis target-domain
Void CacheNull_wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
 
CacheNull_wbInvAll()  // module-wide
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Write back invalidate all caches

C synopsis target-domain
Void CacheNull_wbInvAll();
 
DETAILS
Performs a global write back and invalidate. All cache lines are written out to physical memory and then invalidated.
Module-Wide Built-Ins
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C synopsis target-domain
Types_ModuleId CacheNull_Module_id();
// Get this module's unique id
 
Bool CacheNull_Module_startupDone();
// Test if this module has completed startup
 
IHeap_Handle CacheNull_Module_heap();
// The heap from which this module allocates memory
 
Bool CacheNull_Module_hasMask();
// Test whether this module has a diagnostics mask
 
Bits16 CacheNull_Module_getMask();
// Returns the diagnostics mask for this module
 
Void CacheNull_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module
 
Configuration settings sourced in ti/sysbios/hal/CacheNull.xdc
var CacheNull = xdc.useModule('ti.sysbios.hal.CacheNull');
module-wide constants & types
    values of type CacheNull.Type// Lists of bitmask cache types
        const CacheNull.Type_L1P// Level 1 Program cache;
        const CacheNull.Type_L1D// Level 1 Data cache;
        const CacheNull.Type_L1// Level 1 caches;
        const CacheNull.Type_L2P// Level 2 Program cache;
        const CacheNull.Type_L2D// Level 2 Data cache;
        const CacheNull.Type_L2// Level 2 caches;
        const CacheNull.Type_ALLP// All Program caches;
        const CacheNull.Type_ALLD// All Data caches;
        const CacheNull.Type_ALL// All caches;
module-wide config parameters
    CacheNull.common$// Common module configuration parameters = Types.Common$ undefined;
 
 
enum CacheNull.Type
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Lists of bitmask cache types

Configuration settings
values of type CacheNull.Type
    const CacheNull.Type_L1P;
    // Level 1 Program cache
    const CacheNull.Type_L1D;
    // Level 1 Data cache
    const CacheNull.Type_L1;
    // Level 1 caches
    const CacheNull.Type_L2P;
    // Level 2 Program cache
    const CacheNull.Type_L2D;
    // Level 2 Data cache
    const CacheNull.Type_L2;
    // Level 2 caches
    const CacheNull.Type_ALLP;
    // All Program caches
    const CacheNull.Type_ALLD;
    // All Data caches
    const CacheNull.Type_ALL;
    // All caches
 
C SYNOPSIS
CacheNull_Type
 
metaonly config CacheNull.common$  // module-wide
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Common module configuration parameters

Configuration settings
CacheNull.common$ = Types.Common$ undefined;
 
DETAILS
All modules have this configuration parameter. Its name contains the '$' character to ensure it does not conflict with configuration parameters declared by the module. This allows new configuration parameters to be added in the future without any chance of breaking existing modules.
generated on Tue, 14 Feb 2017 19:58:47 GMT