module ti.sysbios.family.c66.Cache

Cache Module

This Cache module provides C66 family-specific implementations of the APIs defined in ICache. It also provides additional C66 specific cache functions. [ more ... ]
C synopsis target-domain sourced in ti/sysbios/family/c66/Cache.xdc
#include <ti/sysbios/family/c66/Cache.h>
Functions
UInt32 
Void 
Void 
Void 
Void 
Void 
Void 
Functions common to all ICache modules
Void 
Void 
Void 
Void 
Void 
Cache_wb// Writes back a range of memory from all cache(s)(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
Void 
Void 
Void 
Functions common to all target modules
Defines
#define
#define
#define
#define
Typedefs
typedef enum
typedef enum
typedef enum
typedef enum
typedef struct
typedef enum
Constants
extern const Error_Id 
extern const Error_Id 
extern const Bool 
 
DETAILS
This Cache module provides C66 family-specific implementations of the APIs defined in ICache. It also provides additional C66 specific cache functions.
Unconstrained Functions All functions

Calling Context

Function Hwi Swi Task Main Startup
disable Y Y Y Y Y
enable Y Y Y Y Y
getMar* Y Y Y Y Y
getMode* Y Y Y Y Y
getSize* Y Y Y Y Y
inv Y Y Y Y Y
invL1pAll* Y Y Y Y Y
setMar* Y Y Y Y Y
setMode* Y Y Y Y Y
setSize* Y Y Y Y Y
wait Y Y Y Y Y
wb Y Y Y Y Y
wbAll* Y Y Y Y Y
wbL1dAll Y Y Y Y Y
wbInv Y Y Y Y Y
wbInvAll Y Y Y Y Y
wbInvL1dAll Y Y Y Y Y
Definitions:
  • Hwi: API is callable from a Hwi thread.
  • Swi: API is callable from a Swi thread.
  • Task: API is callable from a Task thread.
  • Main: API is callable during any of these phases:
    • In your module startup after this module is started (e.g. Mod_Module_startupDone() returns TRUE).
    • During xdc.runtime.Startup.lastFxns.
    • During main().
    • During BIOS.startupFxns.
  • Startup: API is callable during any of these phases:
    • During xdc.runtime.Startup.firstFxns.
    • In your module startup before this module is started (e.g. Mod_Module_startupDone() returns FALSE).
  • *: These APIs are intended to be made at initialization time, but are not restricted to this.
 
const Cache_PC

Permit Caching

C synopsis target-domain
#define Cache_PC (UInt32)1
 
 
const Cache_PCX

Permit caching in external cache

C synopsis target-domain
#define Cache_PCX (UInt32)4
 
 
const Cache_PFX

Prefetchable by external engines

C synopsis target-domain
#define Cache_PFX (UInt32)8
 
 
const Cache_WTE

Write through enabled

C synopsis target-domain
#define Cache_WTE (UInt32)2
 
 
enum Cache_L1Size

Level 1 cache size type definition. Can be used for both L1D & L1P

C synopsis target-domain
typedef enum Cache_L1Size {
    Cache_L1Size_0K,
    // Amount of cache is 0K, Amount of SRAM is 32K
    Cache_L1Size_4K,
    // Amount of cache is 4K, Amount of SRAM is 28K
    Cache_L1Size_8K,
    // Amount of cache is 8K, Amount of SRAM is 24K
    Cache_L1Size_16K,
    // Amount of cache is 16K, Amount of SRAM is 16K
    Cache_L1Size_32K
    // Amount of cache is 32K, Amount of SRAM is 0K
} Cache_L1Size;
 
 
enum Cache_L2Size

Level 2 cache size type definition

C synopsis target-domain
typedef enum Cache_L2Size {
    Cache_L2Size_0K,
    // L2 is all SRAM
    Cache_L2Size_32K,
    // Amount of cache is 32K
    Cache_L2Size_64K,
    // Amount of cache is 64K
    Cache_L2Size_128K,
    // Amount of cache is 128K
    Cache_L2Size_256K,
    // Amount of cache is 256K
    Cache_L2Size_512K,
    // Amount of cache is 512K
    Cache_L2Size_1024K
    // Amount of cache is 1024K
} Cache_L2Size;
 
 
enum Cache_Mar

MAR register setting type definition

C synopsis target-domain
typedef enum Cache_Mar {
    Cache_Mar_DISABLE,
    // The Permit Copy bit of MAR register is disabled
    Cache_Mar_ENABLE
    // The Permit Copy bit of MAR register is enabled
} Cache_Mar;
 
 
enum Cache_Mode

Lists of cache modes for L1/L2 caches

C synopsis target-domain
typedef enum Cache_Mode {
    Cache_Mode_FREEZE,
    // No new cache lines are allocated
    Cache_Mode_BYPASS,
    // All access result in long-distance access
    Cache_Mode_NORMAL
    // Normal operation of cache
} Cache_Mode;
 
 
enum Cache_Type

Lists of bitmask cache types

C synopsis target-domain
typedef enum Cache_Type {
    Cache_Type_L1P,
    // Level 1 Program cache
    Cache_Type_L1D,
    // Level 1 Data cache
    Cache_Type_L1,
    // Level 1 caches
    Cache_Type_L2P,
    // Level 2 Program cache
    Cache_Type_L2D,
    // Level 2 Data cache
    Cache_Type_L2,
    // Level 2 caches
    Cache_Type_ALLP,
    // All Program caches
    Cache_Type_ALLD,
    // All Data caches
    Cache_Type_ALL
    // All caches
} Cache_Type;
 
 
struct Cache_Size

Structure for specifying all cache sizes

C synopsis target-domain
typedef struct Cache_Size {
    Cache_L1Size l1pSize;
    // L1 Program cache size
    Cache_L1Size l1dSize;
    // L1 Data data size
    Cache_L2Size l2Size;
    // L2 cache size
} Cache_Size;
 
 
config Cache_E_invalidL1CacheSize  // module-wide

Error raised when invalid L1 cache size defined

C synopsis target-domain
extern const Error_Id Cache_E_invalidL1CacheSize;
 
 
config Cache_E_invalidL2CacheSize  // module-wide

Error raised when invalid L2 cache size defined

C synopsis target-domain
extern const Error_Id Cache_E_invalidL2CacheSize;
 
 
config Cache_registerRTSSynch  // module-wide

Boolean flag controlling registration of data synchronization functions that are called by the RTS when accessing shared RTS data objects. The compiler option "--multithread" needs to be applied in order for this feature to be functional (otherwise, empty stubs are used in RTS)

C synopsis target-domain
extern const Bool Cache_registerRTSSynch;
 
 
Cache_disable()  // module-wide

Disables the 'type' cache(s)

C synopsis target-domain
Void Cache_disable(Bits16 type);
 
ARGUMENTS
type — bit mask of Cache type
DETAILS
Disabling of L2 cache is currently not supported.
 
Cache_enable()  // module-wide

Enables all cache(s)

C synopsis target-domain
Void Cache_enable(Bits16 type);
 
ARGUMENTS
type — bit mask of Cache type
 
Cache_getMar()  // module-wide

Gets the MAR register for the specified base address

C synopsis target-domain
UInt32 Cache_getMar(Ptr baseAddr);
 
ARGUMENTS
baseAddr — address for which MAR is requested
RETURNS
value of MAR register
 
Cache_getMode()  // module-wide

Get mode of a cache

C synopsis target-domain
Cache_Mode Cache_getMode(Bits16 type);
 
ARGUMENTS
type — bit mask of cache type
RETURNS
mode of specified level of cache
 
Cache_getSize()  // module-wide

Get sizes of all caches

C synopsis target-domain
Void Cache_getSize(Cache_Size *size);
 
ARGUMENTS
size — pointer to structure of type Cache_Size
 
Cache_inv()  // module-wide

Invalidate the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines in range are invalidated for all the 'type' caches

C synopsis target-domain
Void Cache_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
 
Cache_invL1pAll()  // module-wide

Invalidate all of L1 Program cache

C synopsis target-domain
Void Cache_invL1pAll();
 
DETAILS
Performs a global invalidate of L1P cache. Polls the L1P invalidate register until done.
 
Cache_setMar()  // module-wide

Set MAR register(s) that corresponds to the specified address range

C synopsis target-domain
Void Cache_setMar(Ptr baseAddr, SizeT byteSize, UInt32 value);
 
ARGUMENTS
baseAddr — start address for which to set MAR
byteSize — size (in bytes) of memory block
value — value for setting MAR register
DETAILS
All cached entries in L1 and L2 are written back and invalidated.
All MAR registers that corresponds within the specified base address and base address + size are set to the specified value.
NOTE
The 'wte' (Bit 1) and 'pcx' (Bit 2) MAR bits are reserved on C66x CorePac devices.
 
Cache_setMode()  // module-wide

Set mode of a cache

C synopsis target-domain
Cache_Mode Cache_setMode(Bits16 type, Cache_Mode mode);
 
ARGUMENTS
type — bit mask of cache type
mode — mode of cache
RETURNS
previous mode of cache
 
Cache_setSize()  // module-wide

Set sizes of all caches

C synopsis target-domain
Void Cache_setSize(Cache_Size *size);
 
ARGUMENTS
size — pointer to structure of type Cache_Size
 
Cache_wait()  // module-wide

Wait for a previous cache operation to complete

C synopsis target-domain
Void Cache_wait();
 
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache operation is not truly complete until it has worked its way through all buffering and all memory writes have landed in the source memory.
 
Cache_wb()  // module-wide

Writes back a range of memory from all cache(s)

C synopsis target-domain
Void Cache_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
DETAILS
Writes back the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are left valid in the 'type' caches and the data within the range will be written back to the source memory.
 
Cache_wbAll()  // module-wide

Write back all caches

C synopsis target-domain
Void Cache_wbAll();
 
DETAILS
Perform a global write back. There is no effect on program cache. All data cache lines are left valid.
Perform a global write back. There is no effect on L1P cache. All cache lines are left valid in L1D cache and dirty lines in L1D cache are written back to L2 or external. All cache lines are left valid in L2 cache and dirty lines in L2 cache are written back to external. This function does not wait for write back operation to perculate through the whole memory system before returing. Call Cache_wait(), after this function if necessary.
 
Cache_wbInv()  // module-wide

Writes back and invalidates the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are written back to the source memory and then invalidated for all 'type' caches

C synopsis target-domain
Void Cache_wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
type — bit mask of Cache type
wait — wait until the operation is completed
 
Cache_wbInvAll()  // module-wide

Write back invalidate all caches

C synopsis target-domain
Void Cache_wbInvAll();
 
DETAILS
Performs a global write back and invalidate. All cache lines are written out to physical memory and then invalidated.
Performs a global write back and invalidate. All cache lines are invalidated in L1P cache. All dirty cache lines are written back to L2 or external and then invalidated in L1D cache. All dirty cache lines are written back to external and then invalidated in L2 cache. This function does not wait for write back operation to perculate through the whole memory system before returing. Call Cache_wait(), after this function if necessary.
 
Cache_wbInvL1dAll()  // module-wide

Write back invalidate L1D cache

C synopsis target-domain
Void Cache_wbInvL1dAll();
 
DETAILS
Performs a global write back and invalidate of L1D cache. All dirty cache lines are written back to L2 or external and then invalidated in L1D cache. This function does not wait for write back operation to perculate through the whole memory system before returing. Call Cache_wait(), after this function if necessary.
 
Cache_wbL1dAll()  // module-wide

Write back L1D cache

C synopsis target-domain
Void Cache_wbL1dAll();
 
DETAILS
Perform a global write back of L1D cache. There is no effect on L1P or L2 cache. All cache lines are left valid in L1D cache and the dirty lines in L1D cache are written back to L2 or external. This function does not wait for write back operation to perculate through the whole memory system before returing. Call Cache_wait(), after this function if necessary.
Module-Wide Built-Ins

C synopsis target-domain
Types_ModuleId Cache_Module_id();
// Get this module's unique id
 
Bool Cache_Module_startupDone();
// Test if this module has completed startup
 
IHeap_Handle Cache_Module_heap();
// The heap from which this module allocates memory
 
Bool Cache_Module_hasMask();
// Test whether this module has a diagnostics mask
 
Bits16 Cache_Module_getMask();
// Returns the diagnostics mask for this module
 
Void Cache_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module
 
Configuration settings sourced in ti/sysbios/family/c66/Cache.xdc
var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
module-wide constants & types
    const Cache.PC// Permit Caching = 1;
 
 
        const Cache.L2Size_0K// L2 is all SRAM;
 
 
 
        const Cache.Type_L1D// Level 1 Data cache;
        const Cache.Type_L1// Level 1 caches;
        const Cache.Type_L2D// Level 2 Data cache;
        const Cache.Type_L2// Level 2 caches;
        const Cache.Type_ALLP// All Program caches;
        const Cache.Type_ALLD// All Data caches;
        const Cache.Type_ALL// All caches;
 
        obj.l1pSize// L1 Program cache size = Cache.L1Size  ...
        obj.l1dSize// L1 Data data size = Cache.L1Size  ...
        obj.l2Size// L2 cache size = Cache.L2Size  ...
module-wide config parameters
        msg: "E_invalidL1CacheSize: Invalid L1 cache size %d"
    };
        msg: "E_invalidL2CacheSize: Invalid L2 cache size %d"
    };
 
module-wide functions
    Cache.setMarMeta// Set MAR register(s) that corresponds to the specified address range(Ptr baseAddr, SizeT byteSize, UInt32 value) returns Void
 
 
const Cache.PC

Permit Caching

Configuration settings
const Cache.PC = 1;
 
C SYNOPSIS
 
const Cache.PCX

Permit caching in external cache

Configuration settings
const Cache.PCX = 4;
 
C SYNOPSIS
 
const Cache.PFX

Prefetchable by external engines

Configuration settings
const Cache.PFX = 8;
 
C SYNOPSIS
 
const Cache.WTE

Write through enabled

Configuration settings
const Cache.WTE = 2;
 
C SYNOPSIS
 
enum Cache.L1Size

Level 1 cache size type definition. Can be used for both L1D & L1P

Configuration settings
values of type Cache.L1Size
    const Cache.L1Size_0K;
    // Amount of cache is 0K, Amount of SRAM is 32K
    const Cache.L1Size_4K;
    // Amount of cache is 4K, Amount of SRAM is 28K
    const Cache.L1Size_8K;
    // Amount of cache is 8K, Amount of SRAM is 24K
    const Cache.L1Size_16K;
    // Amount of cache is 16K, Amount of SRAM is 16K
    const Cache.L1Size_32K;
    // Amount of cache is 32K, Amount of SRAM is 0K
 
C SYNOPSIS
 
enum Cache.L2Size

Level 2 cache size type definition

Configuration settings
values of type Cache.L2Size
    const Cache.L2Size_0K;
    // L2 is all SRAM
    const Cache.L2Size_32K;
    // Amount of cache is 32K
    const Cache.L2Size_64K;
    // Amount of cache is 64K
    const Cache.L2Size_128K;
    // Amount of cache is 128K
    const Cache.L2Size_256K;
    // Amount of cache is 256K
    const Cache.L2Size_512K;
    // Amount of cache is 512K
    const Cache.L2Size_1024K;
    // Amount of cache is 1024K
 
C SYNOPSIS
 
enum Cache.Mar

MAR register setting type definition

Configuration settings
values of type Cache.Mar
    const Cache.Mar_DISABLE;
    // The Permit Copy bit of MAR register is disabled
    const Cache.Mar_ENABLE;
    // The Permit Copy bit of MAR register is enabled
 
C SYNOPSIS
 
enum Cache.Mode

Lists of cache modes for L1/L2 caches

Configuration settings
values of type Cache.Mode
    const Cache.Mode_FREEZE;
    // No new cache lines are allocated
    const Cache.Mode_BYPASS;
    // All access result in long-distance access
    const Cache.Mode_NORMAL;
    // Normal operation of cache
 
C SYNOPSIS
 
enum Cache.Type

Lists of bitmask cache types

Configuration settings
values of type Cache.Type
    const Cache.Type_L1P;
    // Level 1 Program cache
    const Cache.Type_L1D;
    // Level 1 Data cache
    const Cache.Type_L1;
    // Level 1 caches
    const Cache.Type_L2P;
    // Level 2 Program cache
    const Cache.Type_L2D;
    // Level 2 Data cache
    const Cache.Type_L2;
    // Level 2 caches
    const Cache.Type_ALLP;
    // All Program caches
    const Cache.Type_ALLD;
    // All Data caches
    const Cache.Type_ALL;
    // All caches
 
C SYNOPSIS
 
struct Cache.Size

Structure for specifying all cache sizes

Configuration settings
var obj = new Cache.Size;
 
    obj.l1pSize = Cache.L1Size  ...
    // L1 Program cache size
    obj.l1dSize = Cache.L1Size  ...
    // L1 Data data size
    obj.l2Size = Cache.L2Size  ...
    // L2 cache size
 
C SYNOPSIS
 
config Cache.E_invalidL1CacheSize  // module-wide

Error raised when invalid L1 cache size defined

Configuration settings
Cache.E_invalidL1CacheSize = Error.Desc {
    msg: "E_invalidL1CacheSize: Invalid L1 cache size %d"
};
 
C SYNOPSIS
 
config Cache.E_invalidL2CacheSize  // module-wide

Error raised when invalid L2 cache size defined

Configuration settings
Cache.E_invalidL2CacheSize = Error.Desc {
    msg: "E_invalidL2CacheSize: Invalid L2 cache size %d"
};
 
C SYNOPSIS
 
config Cache.registerRTSSynch  // module-wide

Boolean flag controlling registration of data synchronization functions that are called by the RTS when accessing shared RTS data objects. The compiler option "--multithread" needs to be applied in order for this feature to be functional (otherwise, empty stubs are used in RTS)

Configuration settings
Cache.registerRTSSynch = Bool false;
 
C SYNOPSIS
 
metaonly config Cache.common$  // module-wide

Common module configuration parameters

Configuration settings
Cache.common$ = Types.Common$ undefined;
 
DETAILS
All modules have this configuration parameter. Its name contains the '$' character to ensure it does not conflict with configuration parameters declared by the module. This allows new configuration parameters to be added in the future without any chance of breaking existing modules.
 
metaonly Cache.getMarMeta()  // module-wide

Gets the current MAR value for the specified base address

Configuration settings
Cache.getMarMeta(Ptr baseAddr) returns UInt32
 
ARGUMENTS
baseAddr — address for which MAR value is requested
RETURNS
MAR value for specified address
 
metaonly Cache.setMarMeta()  // module-wide

Set MAR register(s) that corresponds to the specified address range

Configuration settings
Cache.setMarMeta(Ptr baseAddr, SizeT byteSize, UInt32 value) returns Void
 
ARGUMENTS
baseAddr — start address for which to set MAR
byteSize — size (in bytes) of memory block
value — value for setting MAR register
DETAILS
The 'pc' ("Permit Caching") field is enabled for all memory regions in the device platform. Only set the fields of the Mar structure which need to be modified. Any field not set retains its reset value.
All MAR registers that corresponds within the specified base address and base address + size are set to the specified value.
NOTE
The 'wte' (Bit 1) and 'pcx' (Bit 2) MAR bits are reserved on C66x CorePac devices.
generated on Tue, 14 Feb 2017 19:58:56 GMT