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37
38 package ti.sysbios.family.c64p;
39
40 import xdc.rov.ViewInfo;
41
42 import xdc.runtime.Error;
43
44 /*!
45 * ======== Cache ========
46 * Cache Module
47 *
48 * This Cache module provides C64+ family-specific implementations of the
49 * APIs defined in {@link ti.sysbios.interfaces.ICache ICache}. It also
50 * provides additional C64+ specific cache functions.
51 *
52 * Unconstrained Functions
53 * All functions
54 *
55 * @p(html)
56 * <h3> Calling Context </h3>
57 * <table border="1" cellpadding="3">
58 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
59 *
60 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
61 * <!-- -->
62 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
63 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
64 * <tr><td> {@link #getMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
65 * <tr><td> {@link #getMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
66 * <tr><td> {@link #getSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
67 * <tr><td> {@link #inv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
68 * <tr><td> {@link #invL1pAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
69 * <tr><td> {@link #setMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
70 * <tr><td> {@link #setMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
71 * <tr><td> {@link #setSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
72 * <tr><td> {@link #wait} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
73 * <tr><td> {@link #wb} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
74 * <tr><td> {@link #wbAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
75 * <tr><td> {@link #wbL1dAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
76 * <tr><td> {@link #wbInv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
77 * <tr><td> {@link #wbInvAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
78 * <tr><td> {@link #wbInvL1dAll}</td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
79 * <tr><td colspan="6"> Definitions: <br />
80 * <ul>
81 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
82 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
83 * <li> <b>Task</b>: API is callable from a Task thread. </li>
84 * <li> <b>Main</b>: API is callable during any of these phases: </li>
85 * <ul>
86 * <li> In your module startup after this module is started (e.g. Mod_Module_startupDone() returns TRUE). </li>
87 * <li> During xdc.runtime.Startup.lastFxns. </li>
88 * <li> During main().</li>
89 * <li> During BIOS.startupFxns.</li>
90 * </ul>
91 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
92 * <ul>
93 * <li> During xdc.runtime.Startup.firstFxns.</li>
94 * <li> In your module startup before this module is started (e.g. Mod_Module_startupDone() returns FALSE).</li>
95 * </ul>
96 * <li> <b>*</b>: These APIs are intended to be made at initialization time, but are not restricted to this. </li>
97 * </ul>
98 * </td></tr>
99 *
100 * </table>
101 * @p
102 */
103
104 @ModuleStartup
105
106 module Cache inherits ti.sysbios.interfaces.ICache
107 {
108
109
110 /*!
111 * ======== ModuleView ========
112 * @_nodoc
113 */
114 metaonly struct ModuleView {
115 String L1PCacheSize;
116 String L1PMode;
117 String L1DCacheSize;
118 String L1DMode;
119 String L2CacheSize;
120 String L2Mode;
121 };
122
123 /*!
124 * ======== MarRegisterView ========
125 * @_nodoc
126 */
127 metaonly struct MarRegisterView {
128 UInt number;
129 Ptr addr;
130 Ptr startAddrRange;
131 Ptr endAddrRange;
132 };
133
134 /*!
135 * ======== rovViewInfo ========
136 * @_nodoc
137 */
138 @Facet
139 metaonly config ViewInfo.Instance rovViewInfo =
140 ViewInfo.create({
141 viewMap: [
142 ['Module',
143 {
144 type: ViewInfo.MODULE,
145 viewInitFxn: 'viewInitModule',
146 structName: 'ModuleView'
147 }
148 ],
149 ['EnableMARs',
150 {
151 type: xdc.rov.ViewInfo.MODULE_DATA,
152 viewInitFxn: 'viewInitMarRegisters',
153 structName: 'MarRegisterView'
154 }
155 ]
156 ]
157 });
158
159 /*! Lists of cache modes for L1/L2 caches */
160 enum Mode {
161 Mode_FREEZE, /*! No new cache lines are allocated */
162 Mode_BYPASS, /*! All access result in long-distance access */
163 Mode_NORMAL /*! Normal operation of cache */
164 };
165
166 /*! Level 1 cache size type definition. Can be used for both L1D & L1P */
167 enum L1Size {
168 L1Size_0K = 0, /*! Amount of cache is 0K, Amount of SRAM is 32K */
169 L1Size_4K = 1, /*! Amount of cache is 4K, Amount of SRAM is 28K */
170 L1Size_8K = 2, /*! Amount of cache is 8K, Amount of SRAM is 24K */
171 L1Size_16K = 3, /*! Amount of cache is 16K, Amount of SRAM is 16K */
172 L1Size_32K = 4 /*! Amount of cache is 32K, Amount of SRAM is 0K */
173 };
174
175 /*! Level 2 cache size type definition. */
176 enum L2Size {
177 L2Size_0K = 0, /*! L2 is all SRAM */
178 L2Size_32K = 1, /*! Amount of cache is 32K */
179 L2Size_64K = 2, /*! Amount of cache is 64K */
180 L2Size_128K = 3, /*! Amount of cache is 128K */
181 L2Size_256K = 4, /*! Amount of cache is 256K */
182 L2Size_512K = 5, /*! Amount of cache is 512K */
183 L2Size_1024K = 6 /*! Amount of cache is 1024K */
184 };
185
186 /*! MAR register setting type definition. */
187 enum Mar {
188 Mar_DISABLE = 0, /*! The Permit Copy bit of MAR register is disabled */
189 Mar_ENABLE = 1 /*! The Permit Copy bit of MAR register is enabled */
190 };
191
192 /*! Structure for specifying all cache sizes. */
193 struct Size {
194 L1Size l1pSize; /*! L1 Program cache size */
195 L1Size l1dSize; /*! L1 Data data size */
196 L2Size l2Size; /*! L2 cache size */
197 };
198
199 /*!
200 * Cache sizes.
201 *
202 * When this parameter is set in user's cfg script, user set cache sizes
203 * override those specified by the Cache module or the platform.
204 */
205 config Size initSize = {
206 l1pSize: L1Size_32K,
207 l1dSize: L1Size_32K,
208 l2Size: L2Size_0K
209 };
210
211 /*!
212 * EMIF A configuration address.
213 *
214 * By default, this is set to the physical address. On devices with
215 * a MMU where the physical address is mapped to a virtual address,
216 * the virtual address must be specified here.
217 */
218 config UInt *EMIFA_CFG;
219
220 /*!
221 * EMIF A base register address.
222 *
223 * By default, this is set to the emif A base register physical address.
224 * On devices with a MMU where the physical address is mapped to a virtual
225 * address, the virtual address must be specified here.
226 */
227 config UInt EMIFA_BASE;
228
229 /*!
230 * EMIF A address space length.
231 */
232 config UInt EMIFA_LENGTH;
233
234 /*!
235 * EMIF B configuration address.
236 *
237 * By default, this is set to the physical address. On devices with
238 * a MMU where the physical address is mapped to a virtual address,
239 * the virtual address must be specified here.
240 */
241 config UInt *EMIFB_CFG;
242
243 /*!
244 * EMIF B base register address.
245 *
246 * By default, this is set to the emif B base register physical address.
247 * On devices with a MMU where the physical address is mapped to a virtual
248 * address, the virtual address must be specified here.
249 */
250 config UInt EMIFB_BASE;
251
252 /*!
253 * EMIF B address space length.
254 */
255 config UInt EMIFB_LENGTH;
256
257 /*!
258 * EMIF C configuration address.
259 *
260 * By default, this is set to the physical address. On devices with
261 * a MMU where the physical address is mapped to a virtual address,
262 * the virtual address must be specified here.
263 */
264 config UInt *EMIFC_CFG;
265
266 /*!
267 * EMIF C base register address.
268 *
269 * By default, this is set to the emif C base register physical address.
270 * On devices with a MMU where the physical address is mapped to a virtual
271 * address, the virtual address must be specified here.
272 */
273 config UInt EMIFC_BASE;
274
275 /*!
276 * EMIF C address space length.
277 */
278 config UInt EMIFC_LENGTH;
279
280 /*!
281 * MAR 00 - 31 register bitmask. (for addresses 0x00000000 - 0x1FFFFFFF)
282 *
283 * If undefined by the user, this parameter is configured to match the
284 * memory map of the platform.
285 * Each memory region defined in the platform will have all of its
286 * corresponding MAR bits set.
287 *
288 * To override the default behavior you must initialize this parameter
289 * in your configuration script:
290 *
291 * @p(code)
292 * // disable MAR bits for addresses 0x00000000 to 0x1FFFFFFF
293 * Cache.MAR0_31 = 0x00000000;
294 * @p
295 */
296 config UInt32 MAR0_31;
297
298 /*!
299 * MAR 32 - 63 register bitmask (for addresses 0x20000000 - 0x3FFFFFFF)
300 *
301 * see {@link #MAR0_31} for more info
302 */
303 config UInt32 MAR32_63;
304
305 /*!
306 * MAR 64 - 95 register bitmask (for addresses 0x40000000 - 0x5FFFFFFF)
307 *
308 * see {@link #MAR0_31} for more info
309 */
310 config UInt32 MAR64_95;
311
312 /*!
313 * MAR 96 - 127 register bitmask (for addresses 0x60000000 - 0x7FFFFFFF)
314 *
315 * see {@link #MAR0_31} for more info
316 */
317 config UInt32 MAR96_127;
318
319 /*!
320 * MAR 128 - 159 register bitmask (for addresses 0x80000000 - 0x9FFFFFFF)
321 *
322 * see {@link #MAR0_31} for more info
323 */
324 config UInt32 MAR128_159;
325
326 /*!
327 * MAR 160 - 191 register bitmask (for addresses 0xA0000000 - 0xBFFFFFFF)
328 *
329 * see {@link #MAR0_31} for more info
330 */
331 config UInt32 MAR160_191;
332
333 /*!
334 * MAR 192 - 223 register bitmask (for addresses 0xC0000000 - 0xDFFFFFFF)
335 *
336 * see {@link #MAR0_31} for more info
337 */
338 config UInt32 MAR192_223;
339
340 /*!
341 * MAR 224 - 255 register bitmask (for addresses 0xE0000000 - 0xFFFFFFFF)
342 *
343 * see {@link #MAR0_31} for more info
344 */
345 config UInt32 MAR224_255;
346
347 /*!
348 * Error raised when invalid L1 cache size defined
349 */
350 config Error.Id E_invalidL1CacheSize = {
351 msg: "E_invalidL1CacheSize: Invalid L1 cache size %d"
352 };
353
354 /*!
355 * Error raised when invalid L2 cache size defined
356 */
357 config Error.Id E_invalidL2CacheSize = {
358 msg: "E_invalidL2CacheSize: Invalid L2 cache size %d"
359 };
360
361 /*!
362 * ======== disable ========
363 * Disables the 'type' cache(s)
364 *
365 * Disabling of L2 cache is currently not supported.
366 */
367 override Void disable(Bits16 type);
368
369 /*!
370 * ======== setMode ========
371 * Set mode of a cache
372 *
373 * @param(type) bit mask of cache type
374 * @param(mode) mode of cache
375 *
376 * @b(returns) previous mode of cache
377 */
378 Mode setMode(Bits16 type, Mode mode);
379
380 /*!
381 * ======== getMode ========
382 * Get mode of a cache
383 *
384 * @param(type) bit mask of cache type
385 * @b(returns) mode of specified level of cache
386 */
387 Mode getMode(Bits16 type);
388
389 /*!
390 * ======== setSize ========
391 * Set sizes of all caches
392 *
393 * @param(size) pointer to structure of type Cache_Size
394 */
395 Void setSize(Size *size);
396
397 /*!
398 * ======== getSize ========
399 * Get sizes of all caches
400 *
401 * @param(size) pointer to structure of type Cache_Size
402 */
403 Void getSize(Size *size);
404
405 /*!
406 * ======== getMar ========
407 * Get the value of the MAR register defined for the specified
408 * base address
409 *
410 * @param(baseAddr) address for which MAR is requested
411 *
412 * @b(returns) value of MAR register associated with specified address
413 */
414 Mar getMar(Ptr baseAddr);
415
416 /*!
417 * ======== setMar ========
418 * Set the MAR register(s) that corresponds to the specified
419 * address range.
420 *
421 * @param(baseAddr) start address for which to set MAR
422 * @param(byteSize) size (in bytes) of memory block
423 * @param(value) enum of type Cache_Mar
424 */
425 Void setMar(Ptr baseAddr, SizeT byteSize, Mar value);
426
427 /*!
428 * ======== invL1pAll ========
429 * Invalidate all of L1 Program cache
430 *
431 * Performs a global invalidate of L1P cache.
432 * Polls the L1P invalidate register until done.
433 */
434 Void invL1pAll();
435
436 /*!
437 * ======== wbAll ========
438 * Write back all caches
439 *
440 * Perform a global write back. There is no effect on L1P cache.
441 * All cache lines are left valid in L1D cache and dirty lines in L1D cache
442 * are written back to L2 or external. All cache lines are left valid in
443 * L2 cache and dirty lines in L2 cache are written back to external.
444 * This function does not wait for write back operation to perculate
445 * through the whole memory system before returing. Call Cache_wait(),
446 * after this function if necessary.
447 */
448 override Void wbAll();
449
450 /*!
451 * ======== wbL1dAll ========
452 * Write back L1D cache
453 *
454 * Perform a global write back of L1D cache. There is no effect on L1P
455 * or L2 cache. All cache lines are left valid in L1D cache and the
456 * dirty lines in L1D cache are written back to L2 or external.
457 * This function does not wait for write back operation to perculate
458 * through the whole memory system before returing. Call Cache_wait(),
459 * after this function if necessary.
460 */
461 Void wbL1dAll();
462
463 /*!
464 * ======== wbInvAll ========
465 * Write back invalidate all caches
466 *
467 * Performs a global write back and invalidate. All cache lines are
468 * invalidated in L1P cache. All dirty cache lines are written back to L2
469 * or external and then invalidated in L1D cache. All dirty cache lines
470 * are written back to external and then invalidated in L2 cache.
471 * This function does not wait for write back operation to perculate
472 * through the whole memory system before returing. Call Cache_wait(),
473 * after this function if necessary.
474 */
475 override Void wbInvAll();
476
477 /*!
478 * ======== wbInvL1dAll ========
479 * Write back invalidate L1D cache
480 *
481 * Performs a global write back and invalidate of L1D cache.
482 * All dirty cache lines are written back to L2 or
483 * external and then invalidated in L1D cache.
484 * This function does not wait for write back operation to perculate
485 * through the whole memory system before returing. Call Cache_wait(),
486 * after this function if necessary.
487 */
488 Void wbInvL1dAll();
489
490 internal:
491
492 Void all(volatile UInt32 *cacheReg);
493
494 495 496 497
498 Void block(Ptr blockPtr, SizeT byteCnt, Bool wait,
499 volatile UInt32 *barReg);
500
501 502 503
504 Void getL1DInitSize(Size *size);
505
506 507 508
509 Void getL1PInitSize(Size *size);
510
511 512 513
514 Void getL2InitSize(Size *size);
515
516 517 518 519
520 Void marInit(UInt32 mask, UInt32 index);
521
522
523 const UInt32 L2CFG = 0x01840000;
524 const UInt32 L1PCFG = 0x01840020;
525 const UInt32 L1PCC = 0x01840024;
526 const UInt32 L1DCFG = 0x01840040;
527 const UInt32 L1DCC = 0x01840044;
528 const UInt32 MAR = 0x01848000;
529
530 struct Module_State {
531 volatile UInt32 *emifAddr; /*! Emif configuration address */
532 }
533 }