C6x Register Usage

C6000 DSP/BIOS Register Usage

This document provides tables describing the TMS320C6000TM register conventions in terms of preservation across multi-threaded context switching and preconditions.

Overview

In a multi-threaded application using DSP/BIOS, it is necessary to know which registers can or cannot be modified. Furthermore, users need to understand which registers need to be saved/restored across a function call or an interrupt.

The following definitions describe the various possible register handling behaviors:

  • Scratch register. These registers are saved/restored by the Hwi dispatcher with temporary register bit masks.
  • Preserved register. These registers are saved/restored during a Task context switch.
  • Initialized register. These registers are set to a particular value during Hwi processing and restored to their incoming value upon exiting from the interrupt routine.
  • Read-Only register. These registers may be read but must not be modified.
  • Global register. These registers are shared across all threads in the system. To make a temporary change, save the register, make the change, and then restore it.
  • Other. These registers do not fit into one of the categories above.

Register Conventions

Table 1 Register and Status Bit Handling

Register

Status Bit

Register or Status Bit Name

Type

Notes

A0-A9,
B0-B9

 

General purpose registers

Scratch

 

A10-A12,
A14-A15,
B10-B13

 

General purpose registers

Preserved

 

A13

 

Frame pointer

Preserved

 

B14

 

Data page pointer

Initialized

Hwi sets to bss before calling ISR

B15

 

Stack pointer

Initialized

Hwi sets to Hwi stack before calling ISR

A16-A31**,
B16-B31**

 

General purpose registers

Scratch

 

AMR

 

Addressing mode register

Initialized

Hwi sets to 0 before calling ISR

CSR

GIE

Global interrupt enable

Global

 

 

PGIE

Previous global interrupt enable

Global

 

 

DCC

Data cache control mode

Preserved

 

 

PCC

Program cache control mode

Preserved

 

 

EN

Endian bit

Read-Only

 

 

SAT

Saturation bit

Scratch

 

 

PWRD

Control power-down modes

Global

 

 

Revision ID

Revision ID

Read-Only

 

 

CPU ID

CPU ID

Read-Only

 

IFR

 

Interrupt flag register

Read-Only

 

ISR

 

Interrupt set register

Other

Cannot be read

ICR

 

Interrupt clear register

Other

Cannot be read

IER

 

Interrupt enable register

Read-Only

 

ISTP

 

Interrupt service table pointer

Read-Only

 

IRP

 

Interrupt return pointer

Global

Can be modified with interrupts disabled.

NRP

 

Non-maskable interrupt return pointer

Read-Only

 

PCE1

 

Program counter, E1 phase

Read-Only

 

FADCR*

Rmode

Rounding mode

Global

Currently DSP/BIOS does not deal with this register.

 

UNDER

Underflow status bit

 

 

 

INEX

Exponent status bit

 

 

 

OVER

Overflow status bit

 

 

 

INFO

Signed infinity status bit

 

 

 

INVAL

INVAL status bit

 

 

 

DEN2

Denormalized number

 

 

 

DEN1

Denormalized number

 

 

 

NAN2

NaN number

 

 

 

NAN1

NaN number

 

 

FAUCR*

DIV0

DIV0 status bit

Global

Currently DSP/BIOS does not deal with this register.

 

UNORD

UNORD status bit

 

 

 

UNDER

Underflow status bit

 

 

 

INEX

Exponent status bit

 

 

 

OVER

Overflow status bit

 

 

 

INFO

Signed infinity status bit

 

 

 

INVAL

INVAL status bit

 

 

 

DEN2

Denormalized number

 

 

 

DEN1

Denormalized number

 

 

 

NAN2

NaN number

 

 

 

NAN1

NaN number

 

 

FMCR*

Rmode

Rounding mode

Global

Currently DSP/BIOS does not deal with this register.

 

UNDER

Underflow status bit

 

 

 

INEX

Exponent status bit

 

 

 

OVER

Overflow status bit

 

 

 

INFO

Signed infinity status bit

 

 

 

INVAL

INVAL status bit

 

 

 

DEN2

Denormalized number

 

 

 

DEN1

Denormalized number

 

 

 

NAN2

NaN number

 

 

 

NAN1

NaN number

 

 

GFPGFR**

 

Galois Field Polynomial
Generator

Global

Currently DSP/BIOS does not deal with this register.

TSR+

GIE

Global interrupt enable

Global

 

 

SGIE

Saved global interrupt enable

Global

 

 

GEE

Global exception enable

Read-Only

 

 

XEN

Maskable exception enable

Read-Only

 

 

DBGM

Emulator debug mask

Read-Only

 

 

CXM

Current execution mode

Read-Only

 

 

INT

Interrupt processing

Read-Only / Other

DSP/BIOS does not maintain this C64x+ status bit. Since DSP/BIOS does not do a "return from interrupt" for certain task switches, your application should not expect this bit to correctly indicate whether an interrupt is currently being processed.

 

EXC

Exception processing

Read-Only

 

 

SPLX

SPLOOP executing

Read-Only

 

 

IB

Interrupt blocked

Read-Only

 

ITSR+

 

Interrupt task state register

Global

 

NTSR+

 

NMI/Exception task state register

Global

 

EFR+

 

Exception flag register

Read-Only

 

ECR+

 

Exception clear register

Read-Only

 

IERR+

 

Internal exception cause register

Read-Only

 

SSR+

 

Saturation status register

Global

 

ILC+

 

Inner loop SPL buffer count

Global

 

RILC+

 

Reload inner loop SPL buffer count

Global

 

GPLYA+

 

GMPY polynomial for A side

Scratch, Preserve

 

GPLYB+

 

GMPY polynomial for B side

Scratch, Preserve

 

TSCL+

 

Low half of 64-bit time stamp counter

Read-Only

 

TSCH+

 

High half of 64-bit time stamp counter

Read-Only

 

DNUM+

 

DSP number

Read-Only

 

DIER+

 

Debug interrupt enable register

Global

 

Notes:

* - Denotes registers available on the `C67x, `C67x+ to support floating point operations.

** - Denotes registers available on the `C64x, `C67x+ only.

+ - Denotes registers available on the `C64x+ only.

The General purpose registers follow the 'C' compiler conventions. IRP can be used as a scratch register only when interrupts are disabled. ITSR and NTSR are identical copies of TSR, see TSR for details on each individual status bit.

For the `C67x FADCR, FAUCR, and FMCR registers, the compiler assumes the nearest rounding mode is used. This is assumed to be the default mode at power-up. The compiler does not actually do anything to set it up that way, nor does it ever write or read these registers. These registers are completely under user control. Code may generate slightly different results if you change these registers.