1 /*
2 * Copyright (c) 2013, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /*
33 * ======== Cache.xdc ========
34 *
35 *
36 */
37
38 package ti.sysbios.family.arp32;
39
40 import xdc.runtime.Assert;
41 import xdc.rov.ViewInfo;
42
43 /*!
44 * ======== Cache ========
45 * Cache Module
46 *
47 * This Cache module provides ARP32 family-specific implementations of the
48 * APIs defined in {@link ti.sysbios.interfaces.ICache ICache}. It also
49 * provides additional ARP32 specific cache functions.
50 *
51 * Unconstrained Functions
52 * All functions
53 *
54 * @p(html)
55 * <h3> Calling Context </h3>
56 * <table border="1" cellpadding="3">
57 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
58 *
59 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
60 * <!-- -->
61 * <tr><td> {@link #inv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
62 * <tr><td> {@link #invL1pAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
63 * <tr><td> {@link #invL1pSingleAddr} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
64 * <tr><td> {@link #preloadL1p} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
65 * <tr><td colspan="6"> Definitions: <br />
66 * <ul>
67 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
68 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
69 * <li> <b>Task</b>: API is callable from a Task thread. </li>
70 * <li> <b>Main</b>: API is callable during any of these phases: </li>
71 * <ul>
72 * <li> In your module startup after this module is started (e.g. Mod_Module_startupDone() returns TRUE). </li>
73 * <li> During xdc.runtime.Startup.lastFxns. </li>
74 * <li> During main().</li>
75 * <li> During BIOS.startupFxns.</li>
76 * </ul>
77 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
78 * <ul>
79 * <li> During xdc.runtime.Startup.firstFxns.</li>
80 * <li> In your module startup before this module is started (e.g. Mod_Module_startupDone() returns FALSE).</li>
81 * </ul>
82 * <li> <b>*</b>: These APIs are intended to be made at initialization time, but are not restricted to this. </li>
83 * </ul>
84 * </td></tr>
85 *
86 * </table>
87 * @p
88 */
89
90 module Cache inherits ti.sysbios.interfaces.ICache
91 {
92 /*!
93 * Assert raised when byte count is too large
94 */
95 config Assert.Id A_byteCountTooLarge = {
96 msg: "A_byteCountTooLarge: byte count is too large"
97 };
98
99 /*!
100 * ======== invL1pAll ========
101 * Invalidate all of L1 Program cache
102 *
103 * Performs a global invalidate of L1P cache.
104 * Polls the L1P invalidate register until operation is complete.
105 */
106 Void invL1pAll();
107
108 /*!
109 * ======== invL1pSingleAddr ========
110 * Invalidate a single address in L1 Program Cache
111 */
112 Void invL1pSingleAddr(Ptr blockPtr);
113
114 /*!
115 * ======== preloadL1p ========
116 * Preload the L1 Program cache range
117 */
118 Void preloadL1p(Ptr blockPtr, SizeT byteCnt);
119
120
121 internal:
122
123 /*
124 * ======== block ========
125 * This internal function is used by the block cache APIs.
126 */
127 Void block(Ptr blockPtr, SizeT byteCnt, Bool wait,
128 volatile UInt32 *barReg, volatile UInt32 *countReg);
129
130 }