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33 34 35 36
37 package ti.sysbios.family.arm.m3;
38
39 import xdc.rov.ViewInfo;
40 import xdc.runtime.Diags;
41 import xdc.runtime.Log;
42 import xdc.runtime.Assert;
43 import xdc.runtime.Error;
44
45 import ti.sysbios.BIOS;
46 import ti.sysbios.interfaces.IHwi;
47
48 /*!
49 * ======== Hwi ========
50 * Cortex M3 Hardware Interrupt Manager
51 *
52 * The Cortex M3's Nested Vectored Interrupt Controller (NVIC)
53 * supports up to 256 interrupts/exceptions. In practice, most
54 * devices support much fewer (ie the Stellaris family of devices
55 * have only 80 total interrupts defined).
56 *
57 * SYS/BIOS Interrupt IDs or interrupt numbers correspond
58 * to an interrupt's position in the interrupt vector table.
59 *
60 * ID 0 corresponds to vector 0 which is used by the NVIC
61 * to hold the initial (reset) stack pointer value.
62 *
63 * ID 1 corresponds to vector 1 which is the reset vector (ie _c_int00)
64 *
65 * IDs 2-14 are hardwired to exceptions.
66 *
67 * ID 15 is the SysTick timer interrupt.
68 *
69 * ID's 16-255 are mapped to the NVIC's user interrupts 0-239
70 * which are tied to platform specific interrupt sources.
71 *
72 * @a(Zero Latency Interrupts)
73 * The M3 Hwi module supports "zero latency" interrupts.
74 * Interrupts configured with priority greater (in actual
75 * hardware priority, but lower in number) than
76 * {@link #disablePriority Hwi.disablePriority} are NOT
77 * disabled by Hwi_disable().
78 *
79 * Zero latency interrupts are distinguished from regular dispatched
80 * interrupts at create time by their priority being greater
81 * than Hwi.disablePriority.
82 *
83 * Note that since zero latency interrupts don't use the dispatcher,
84 * the {@link ti.sysbios.interfaces.IHwi#arg arg} parameter is not
85 * functional. Also note that due to the M3's native automatic
86 * stacking of saved-by-caller C context on the way to an ISR, zero
87 * latency interrupt handlers are implemented using regular C functions
88 * (ie no 'interrupt' keyword is required).
89 *
90 * @a(WARNING)
91 * Zero latency interrupts are NOT HANDLED by the SYS/BIOS
92 * interrupt dispatcher! Instead, they are vectored to directly.
93 * As such, and because they are NOT DISABLED BY Hwi_disable(),
94 * these interrupt handlers are SEVERELY RESTRICTED in terms of the
95 * SYS/BIOS APIs they can invoke and THREAD SAFETY MUST BE CAREFULLY
96 * CONSIDERED! See the descriptions of {@link #disable Hwi_disable()} and
97 * and {@link #disablePriority Hwi.disablePriority} for more details.
98 *
99 * @a(Interrupt Masking Options)
100 *
101 * The NVIC interrupt controller is designed for priority based
102 * interrupts.
103 *
104 * In this Hwi module, the {@link #maskSetting} instance configuration
105 * parameter is ignored.
106 * Effectively, only the {@link #MaskingOption_LOWER} is supported.
107 *
108 * @a(Interrupt Priorities)
109 *
110 * In general, the NVIC supports priority values of 0 thru 255.
111 *
112 * In practice, the number of priorities and their values are device
113 * dependent, and their nesting behaviors depend on the
114 * {@link #priGroup Hwi.priGroup} setting.
115 *
116 * For most TI MCU devices, 8 priorities are supported. A peculiarity
117 * of ARM's NVIC is that, although the priority field is an 8 bit value,
118 * the range of supported priority values are left-justified within this
119 * 8 bit field. Consequently, the 8 priority values are not 0 thru 7 as
120 * one might expect, but rather:
121 *
122 * @p(code)
123 * 0x00 // highest priority, non dispatched, Zero Latency priority
124 * 0x20 // highest dispatched interrupt priority
125 * 0x40
126 * 0x60
127 * 0x80
128 * 0xa0
129 * 0xc0
130 * 0xe0 // lowest dispatched interrupt priority, (default)
131 * @p
132 *
133 * Priority 0 is the highest priority and by default is
134 * reserved for zero latency interrupts
135 * (see {@link #disablePriority Hwi.disablePriority}).
136 *
137 * See the Cortex M3 architecture reference manual for details
138 * on the behavior of interrupt priorities and their relationship
139 * to the {@link #priGroup Hwi.priGroup} setting.
140 *
141 * @a(Interrupt Vector Tables)
142 * Tiva devices:
143 *
144 * By default, two vector tables are created for Tiva devices:
145 *
146 * A 16 entry boot vector table is placed at address 0x00000000 in
147 * FLASH.
148 *
149 * An 80 entry vector table is placed at address 0x20000000 in RAM.
150 *
151 * The FLASH boot vector table contains the reset vector and exception
152 * handler vectors used until the RAM based vector table is initialized.
153 *
154 * The RAM vector table contains the 16 exception vectors as well as all
155 * the 64 user interrupt vectors.
156 *
157 * During system startup, the NVIC Vector Table Offset Registor is
158 * intialized to point to this vector table after the table has been
159 * initialized.
160 *
161 * @a( )
162 * Dual M3 Core ('Ducati') devices:
163 *
164 * By default, Ducati core 0 places its runtime vector table at address
165 * 0x00000400 and core 1 places its runtime vector table at address
166 * 0x00000800.
167 *
168 * Additionally, a boot vector table is placed at address
169 * 0x00000000 which is shared by both cores.
170 *
171 * The boot reset vector function determines which core it is being
172 * executed on and jumps to the reset vector contained in its corresponding
173 * runtime vector table.
174 *
175 * The generation and placement of these vector tables is made
176 * automatically when the
177 * {@link ti.sysbios.family.arm.ducati.Core} module is used.
178 *
179 * Although STRONGLY discouraged, this default behavior can be overridden
180 * by explicitly setting the
181 * {@link #resetVectorAddress Hwi.resetVectorAddress} and
182 * {@link #vectorTableAddress Hwi.vectorTableAddress} config parameters.
183 *
184 * @a(Restrictions)
185 * When used within a dual M3 core (Ducati) arrangement, care must be
186 * taken when initializing this shared resource.
187 * The "Shared Resources" note provided
188 * in the {@link ti.sysbios.family.arm.ducati ducati} package discusses
189 * the management of the various hardware and software resources
190 * shared by the two M3 cores.
191 * @a
192 *
193 * @p(html)
194 * <h3> Calling Context </h3>
195 * <table border="1" cellpadding="3">
196 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
197 *
198 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
199 * <!-- -->
200 * <tr><td> {@link #clearInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
201 * <tr><td> {@link #create} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
202 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
203 * <tr><td> {@link #disableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
204 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> N </td><td> N </td></tr>
205 * <tr><td> {@link #enableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
206 * <tr><td> {@link #Params_init} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
207 * <tr><td> {@link #restore} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
208 * <tr><td> {@link #restoreInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
209 * <tr><td> {@link #construct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
210 * <tr><td> {@link #delete} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
211 * <tr><td> {@link #destruct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
212 * <tr><td> {@link #getHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
213 * <tr><td> {@link #setFunc} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
214 * <tr><td> {@link #setHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
215 * <tr><td colspan="6"> Definitions: <br />
216 * <ul>
217 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
218 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
219 * <li> <b>Task</b>: API is callable from a Task thread. </li>
220 * <li> <b>Main</b>: API is callable during any of these phases: </li>
221 * <ul>
222 * <li> In your module startup after this module is started (e.g. Hwi_Module_startupDone() returns TRUE). </li>
223 * <li> During xdc.runtime.Startup.lastFxns. </li>
224 * <li> During main().</li>
225 * <li> During BIOS.startupFxns.</li>
226 * </ul>
227 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
228 * <ul>
229 * <li> During xdc.runtime.Startup.firstFxns.</li>
230 * <li> In your module startup before this module is started (e.g. Hwi_Module_startupDone() returns FALSE).</li>
231 * </ul>
232 * </ul>
233 * </td></tr>
234 *
235 * </table>
236 * @p
237 */
238
239
240 @Template("./Hwi.xdt")
241 @ModuleStartup
242 @InstanceInitStatic
243
244 module Hwi inherits ti.sysbios.interfaces.IHwi
245 {
246
247
248 /*!
249 * The Cortex M3 NVIC supports up to 256 interrupts/exceptions.
250 *
251 * The actual number supported is device specific and provided by
252 * the catalog device specification.
253 */
254 config Int NUM_INTERRUPTS;
255
256 /*!
257 * The Cortex M3 NVIC supports up to 256 interrupt priorities.
258 *
259 * The actual number supported is device specific and provided by
260 * the catalog device specification.
261 */
262 config Int NUM_PRIORITIES;
263
264
265
266 /*! Hwi vector function type definition. */
267 typedef Void (*VectorFuncPtr)(void);
268
269 /*! Exception hook function type definition. */
270 typedef Void (*ExceptionHookFuncPtr)(ExcContext *);
271
272 /*! NVIC Configuration Control Register (CCR). */
273 struct CCR {
274 Bits8 STKALIGN; /*! Auto stack alignment in exception */
275 Bits8 BFHFNMIGN; /*! All faults ignore BUS Faults */
276 Bits8 DIV_0_TRP; /*! Trap on divide by zero */
277 Bits8 UNALIGN_TRP; /*! Trap on all unaligned accesses */
278 Bits8 USERSETMPEND; /*! Allow user to trigger interrupts */
279 Bits8 NONEBASETHRDENA; /*! Allow entering thread mode anytime */
280 };
281
282 /*! @_nodoc
283 * Nested Vectored Interrupt Controller.
284 */
285 struct NVIC {
286 UInt32 RES_00; /*! 0xE000E000 reserved */
287 UInt32 ICTR; /*! 0xE000E004 Interrupt Control Type */
288 UInt32 RES_08; /*! 0xE000E008 reserved */
289 UInt32 RES_0C; /*! 0xE000E00C reserved */
290 UInt32 STCSR; /*! 0xE000E010 SysTick Control & Status Register */
291 UInt32 STRVR; /*! 0xE000E014 SysTick Reload Value Register */
292 UInt32 STCVR; /*! 0xE000E018 SysTick Current Value Register */
293 UInt32 STCALIB; /*! 0xE000E01C SysTick Calibration Value Register */
294 UInt32 RES_20 [56]; /*! 0xE000E020-0xE000E0FC reserved */
295 UInt32 ISER [8]; /*! 0xE000E100-0xE000E11C Interrupt Set Enable Registers */
296 UInt32 RES_120 [24]; /*! 0xE000E120-0xE000E17C reserved */
297 UInt32 ICER [8]; /*! 0xE000E180-0xE000E19C Interrupt Clear Enable Registers */
298 UInt32 RES_1A0 [24]; /*! 0xE000E1A0-0xE000E1FC reserved */
299 UInt32 ISPR [8]; /*! 0xE000E200-0xE000E21C Interrupt Set Pending Registers */
300 UInt32 RES_220 [24]; /*! 0xE000E220-0xE000E7C reserved */
301 UInt32 ICPR [8]; /*! 0xE000E280-0xE000E29C Interrupt Clear Pending Registers */
302 UInt32 RES_2A0 [24]; /*! 0xE000E2A0-0xE000E2FC reserved */
303 UInt32 IABR [8]; /*! 0xE000E300-0xE000E31C Interrupt Active Bit Registers */
304 UInt32 RES_320 [56]; /*! 0xE000E320-0xE000E3FC reserved */
305 UInt8 IPR [240]; /*! 0xE000E400-0xE000E4EF Interrupt Priority Registers */
306 UInt32 RES_4F0 [516];/*! 0xE000E4F0-0xE000ECFC reserved */
307 UInt32 CPUIDBR; /*! 0xE000ED00 CPUID Base Register */
308 UInt32 ICSR; /*! 0xE000ED04 Interrupt Control State Register */
309 UInt32 VTOR; /*! 0xE000ED08 Vector Table Offset Register */
310 UInt32 AIRCR; /*! 0xE000ED0C Application Interrupt/Reset Control Register */
311 UInt32 SCR; /*! 0xE000ED10 System Control Register */
312 UInt32 CCR; /*! 0xE000ED14 Configuration Control Register */
313 UInt8 SHPR[12]; /*! 0xE000ED18 System Handlers 4-15 Priority Registers */
314 UInt32 SHCSR; /*! 0xE000ED24 System Handler Control & State Register */
315 UInt8 MMFSR; /*! 0xE000ED28 Memory Manage Fault Status Register */
316 UInt8 BFSR; /*! 0xE000ED29 Bus Fault Status Register */
317 UInt16 UFSR; /*! 0xE000ED2A Usage Fault Status Register */
318 UInt32 HFSR; /*! 0xE000ED2C Hard Fault Status Register */
319 UInt32 DFSR; /*! 0xE000ED30 Debug Fault Status Register */
320 UInt32 MMAR; /*! 0xE000ED34 Memory Manager Address Register */
321 UInt32 BFAR; /*! 0xE000ED38 Bus Fault Address Register */
322 UInt32 AFSR; /*! 0xE000ED3C Auxiliary Fault Status Register */
323 UInt32 PFR0; /*! 0xE000ED40 Processor Feature Register */
324 UInt32 PFR1; /*! 0xE000ED44 Processor Feature Register */
325 UInt32 DFR0; /*! 0xE000ED48 Debug Feature Register */
326 UInt32 AFR0; /*! 0xE000ED4C Auxiliary Feature Register */
327 UInt32 MMFR0; /*! 0xE000ED50 Memory Model Fault Register0 */
328 UInt32 MMFR1; /*! 0xE000ED54 Memory Model Fault Register1 */
329 UInt32 MMFR2; /*! 0xE000ED58 Memory Model Fault Register2 */
330 UInt32 MMFR3; /*! 0xE000ED5C Memory Model Fault Register3 */
331 UInt32 ISAR0; /*! 0xE000ED60 ISA Feature Register0 */
332 UInt32 ISAR1; /*! 0xE000ED64 ISA Feature Register1 */
333 UInt32 ISAR2; /*! 0xE000ED68 ISA Feature Register2 */
334 UInt32 ISAR3; /*! 0xE000ED6C ISA Feature Register3 */
335 UInt32 ISAR4; /*! 0xE000ED70 ISA Feature Register4 */
336 UInt32 RES_D74[5]; /*! 0xE000ED74-0xE000ED84 reserved */
337 UInt32 CPACR; /*! 0xE000ED88 Coprocessor Access Control Register */
338 UInt32 RES_D8C[93]; /*! 0xE000ED8C-0xE000EEFC reserved */
339 UInt32 STI; /*! 0xE000EF00 Software Trigger Interrupt Register */
340 UInt32 RES_F04[12]; /*! 0xE000EF04-0xE000EF30 reserved */
341 UInt32 FPCCR; /*! 0xE000EF34 FP Context Control Register */
342 UInt32 FPCAR; /*! 0xE000EF38 FP Context Address Register */
343 UInt32 FPDSCR; /*! 0xE000EF3C FP Default Status Control Register */
344 UInt32 MVFR0; /*! 0xE000EF40 Media & FP Feature Register0 */
345 UInt32 MVFR1; /*! 0xE000EF44 Media & FP Feature Register1 */
346 UInt32 RES_F48[34]; /*! 0xE000EF48-0xE000EFCC reserved */
347 UInt32 PID4; /*! 0xE000EFD0 Peripheral ID Register4 */
348 UInt32 PID5; /*! 0xE000EFD4 Peripheral ID Register5 */
349 UInt32 PID6; /*! 0xE000EFD8 Peripheral ID Register6 */
350 UInt32 PID7; /*! 0xE000EFDC Peripheral ID Register7 */
351 UInt32 PID0; /*! 0xE000EFE0 Peripheral ID Register0 */
352 UInt32 PID1; /*! 0xE000EFE4 Peripheral ID Register1 */
353 UInt32 PID2; /*! 0xE000EFE8 Peripheral ID Register2 */
354 UInt32 PID3; /*! 0xE000EFEC Peripheral ID Register3 */
355 UInt32 CID0; /*! 0xE000EFF0 Component ID Register0 */
356 UInt32 CID1; /*! 0xE000EFF4 Component ID Register1 */
357 UInt32 CID2; /*! 0xE000EFF8 Component ID Register2 */
358 UInt32 CID3; /*! 0xE000EFFC Component ID Register3 */
359 }
360
361 /*!
362 * Physical Nested Vectored Interrupt Controller Device.
363 * Short name is "Hwi_nvic"
364 * Long name is "ti_sysbios_family_arm_m3_Hwi_nvic"
365 */
366 extern volatile NVIC nvic;
367
368 /*!
369 * Virtual Nested Vectored Interrupt Controller structure
370 * written to by both cores for SMP.
371 * Short name is "Hwi_vnvic"
372 * Long name is "ti_sysbios_family_arm_m3_Hwi_vnvic"
373 */
374 extern volatile NVIC vnvic;
375
376 /*!
377 * Exception Context - Register contents at the time of an exception.
378 */
379 struct ExcContext {
380
381 BIOS.ThreadType threadType;
382
383 Ptr threadHandle;
384
385 Ptr threadStack;
386
387
388 SizeT threadStackSize;
389
390
391 Ptr r0;
392 Ptr r1;
393 Ptr r2;
394 Ptr r3;
395 Ptr r4;
396 Ptr r5;
397 Ptr r6;
398 Ptr r7;
399 Ptr r8;
400 Ptr r9;
401 Ptr r10;
402 Ptr r11;
403 Ptr r12;
404 Ptr sp;
405 Ptr lr;
406 Ptr pc;
407 Ptr psr;
408
409
410 Ptr ICSR;
411 Ptr MMFSR;
412 Ptr BFSR;
413 Ptr UFSR;
414 Ptr HFSR;
415 Ptr DFSR;
416 Ptr MMAR;
417 Ptr BFAR;
418 Ptr AFSR;
419 }
420
421 /*! @_nodoc */
422 metaonly struct BasicView {
423 Ptr halHwiHandle;
424 String label;
425 String type;
426 Int intNum;
427 Int priority;
428 Int group;
429 Int subPriority;
430 String fxn;
431 UArg arg;
432 };
433
434 /*! @_nodoc */
435 metaonly struct DetailedView {
436 Ptr halHwiHandle;
437 String label;
438 String type;
439 Int intNum;
440 Int priority;
441 Int group;
442 Int subPriority;
443 String fxn;
444 UArg arg;
445 Ptr irp;
446 String status;
447 Int coreId;
448 };
449
450 /*! @_nodoc */
451 metaonly struct ModuleView {
452 String options[4];
453 String activeInterrupt;
454 String pendingInterrupt;
455 String exception;
456 String hwiStackPeak;
457 SizeT hwiStackSize;
458 Ptr hwiStackBase;
459 };
460
461 /*! @_nodoc */
462 @Facet
463 metaonly config ViewInfo.Instance rovViewInfo =
464 ViewInfo.create({
465 viewMap: [
466 ['Basic',
467 {
468 type: ViewInfo.INSTANCE,
469 viewInitFxn: 'viewInitBasic',
470 structName: 'BasicView'
471 }
472 ],
473 ['Detailed',
474 {
475 type: ViewInfo.INSTANCE,
476 viewInitFxn: 'viewInitDetailed',
477 structName: 'DetailedView'
478 }
479 ],
480 ['Module',
481 {
482 type: ViewInfo.MODULE,
483 viewInitFxn: 'viewInitModule',
484 structName: 'ModuleView'
485 }
486 ],
487 ['Exception',
488 {
489 type: ViewInfo.TREE,
490 viewInitFxn: 'viewInitException',
491 structName: 'ExcContext'
492 }
493 ]
494 ]
495 });
496
497
498
499
500
501 /*!
502 * Issued just prior to Hwi function invocation (with interrupts disabled)
503 */
504 config Log.Event LM_begin = {
505 mask: Diags.USER1 | Diags.USER2,
506 msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
507 };
508
509 /*!
510 * Issued just after return from Hwi function (with interrupts disabled)
511 */
512 config Log.Event LD_end = {
513 mask: Diags.USER2,
514 msg: "LD_end: hwi: 0x%x"
515 };
516
517
518
519 /*! Assert when bad maskSetting parameter provided */
520 config Assert.Id A_unsupportedMaskingOption = {
521 msg: "A_unsupportedMaskingOption: unsupported maskSetting."
522 };
523
524
525
526 /*!
527 * Error raised when Hwi is already defined
528 */
529 config Error.Id E_alreadyDefined = {
530 msg: "E_alreadyDefined: Hwi already defined: intr# %d"
531 };
532
533 /*!
534 * Error raised when the number of interrupts being created
535 * exceeds the number supported.
536 */
537 config Error.Id E_hwiLimitExceeded = {
538 msg: "E_hwiLimitExceeded: Too many interrupts defined"
539 };
540
541 /*!
542 * Error raised when an exception occurs
543 */
544 config Error.Id E_exception = {
545 msg: "E_exception: id = %d, pc = %08x.\nTo see more exception detail, set ti.sysbios.family.arm.m3.Hwi.enableException = true or,\nexamine the Exception view for the ti.sysbios.family.arm.m3.Hwi module using ROV."
546 };
547
548 /*!
549 * Error raised when an uninitialized interrupt occurs
550 */
551 config Error.Id E_noIsr = {
552 msg: "E_noIsr: id = %d, pc = %08x"
553 };
554
555 /*!
556 * Error raised when NMI exception occurs
557 */
558 config Error.Id E_NMI = {
559 msg: "E_NMI: %s"
560 };
561
562 /*!
563 * Error raised when hard fault exception occurs
564 */
565 config Error.Id E_hardFault = {
566 msg: "E_hardFault: %s"
567 };
568
569 /*!
570 * Error raised when memory fault exception occurs
571 */
572 config Error.Id E_memFault = {
573 msg: "E_memFault: %s, address: %08x"
574 };
575
576 /*!
577 * Error raised when bus fault exception occurs
578 */
579 config Error.Id E_busFault = {
580 msg: "E_busFault: %s, address: %08x"
581 };
582
583 /*!
584 * Error raised when usage fault exception occurs
585 */
586 config Error.Id E_usageFault = {
587 msg: "E_usageFault: %s"
588 };
589
590 /*!
591 * Error raised when svCall exception occurs
592 */
593 config Error.Id E_svCall = {
594 msg: "E_svCall: svNum = %d"
595 };
596
597 /*!
598 * Error raised when debugMon exception occurs
599 */
600 config Error.Id E_debugMon = {
601 msg: "E_debugMon: %s"
602 };
603
604 /*!
605 * Error raised when reserved exception occurs
606 */
607 config Error.Id E_reserved = {
608 msg: "E_reserved: %s %d"
609 };
610
611
612
613 /*!
614 * Size (in number of interrupts) of the table used by the interrupt
615 * dispatcher to locate the corresponding Hwi object. By default,
616 * Hwi.dispatchTableSize will be internally set
617 * to the number of interrupts supported by the device.
618 *
619 * When the Hwi dispatch table size is equal to the number of interrupts
620 * supported {@link #NUM_INTERRUPTS} by the device, a linear-indexed
621 * dispatch table mechanism is used that will consume 4 bytes of RAM
622 * for each interrupt supported.
623 *
624 * If the dispatch table size is set to a number less than the number
625 * of interrupts supported by the device, then a non linear-indexed
626 * dispatch table mechanism is employed that uses 12 bytes of RAM for
627 * each interrupt supported.
628 *
629 * Consequently, for applications that use less than 1/3 of the total
630 * number of interrupts supported by the device, setting this parameter
631 * to the number of interrupts ACTUALLY USED will result in less RAM
632 * memory being used than otherwise.
633 *
634 * For applications that use very few interrupts, this can be a significant RAM memory savings.</p>
635 */
636 metaonly config UInt dispatchTableSize;
637
638 /*!
639 * Location of the Runtime Interrupt Vector Table.
640 * Default is device dependent.
641 *
642 * This parameter allows the user to override the default placement
643 * of the runtime interrupt vector table.
644 * The NVIC's Vector Table Offset
645 * Register (VTOR) is also programmed to this value.
646 *
647 * Some systems require the runtime vector table to be placed at
648 * an address
649 * other than 0 but still need a copy of the two M3 boot vectors
650 * (SP and reset PC), located there. To achieve this, a separate
651 * parameter {@link #resetVectorAdress} is provided. If the
652 * resetVectorAddress has a different value then the vectorTableAddress
653 * then a separate vector table is generated and placed at that
654 * address.
655 *
656 * The vector table must be placed at an address at or lower than
657 * 0x3FFFFC00 and must be aligned on an even 64 word boundary.
658 */
659 metaonly config Ptr vectorTableAddress = 0x00000000;
660
661 /*!
662 * Reset vector table address. Default is 0x00000000.
663 *
664 * This parameter is the address of the vector table used
665 * at system reset time. Typically this is placed at 0x00000000.
666 *
667 * If the Hwi.resetVectorAddress has a different value than
668 * the {@link #vectorTableAddress Hwi.vectorTableAddress}
669 * then two vector tables are generated, one at the Hwi.resetVectorAddress
670 * and another at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
671 *
672 * After the initial boot code has been executed at startup, the NVIC's
673 * Vector Table Offset Register will be programmed to point to the
674 * vector table at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
675 *
676 * is created and placed in the ".resetVecs" section.
677 */
678 metaonly config Ptr resetVectorAddress = 0x00000000;
679
680 /*! Reset Handler. Default is c_int00 */
681 metaonly config VectorFuncPtr resetFunc;
682
683 /*! NMI Handler. Default is set to an internal exception handler */
684 metaonly config VectorFuncPtr nmiFunc;
685
686 /*! Hard Fault Handler. Default is set to an internal exception handler */
687 metaonly config VectorFuncPtr hardFaultFunc;
688
689 /*! Hard Mem Handler. Default is set to an internal exception handler */
690 metaonly config VectorFuncPtr memFaultFunc;
691
692 /*! Bus Fault Handler. Default is set to an internal exception handler */
693 metaonly config VectorFuncPtr busFaultFunc;
694
695 /*! Usage Fault Handler. Default is set to an internal exception handler */
696 metaonly config VectorFuncPtr usageFaultFunc;
697
698 /*! SVCall Handler. Default is set to an internal exception handler */
699 metaonly config VectorFuncPtr svCallFunc;
700
701 /*! Debug Mon Handler. Default is set to an internal exception handler */
702 metaonly config VectorFuncPtr debugMonFunc;
703
704 /*! Reserved Exception Handler. Default is set to an internal exception handler */
705 metaonly config VectorFuncPtr reservedFunc;
706
707 /*! Uninitialized ISR Handler. Default is set to an internal exception handler */
708 config VectorFuncPtr nullIsrFunc;
709
710 /*! Hwi exception handler function type definition. */
711 typedef Void (*ExcHandlerFuncPtr)(UInt *, UInt);
712
713 /*!
714 * Exception handler function pointer.
715 *
716 * The default is determined by the value of Hwi.enableException.
717 *
718 * If the user does NOT set this parameter, then the following default
719 * behavior is followed:
720 *
721 * If Hwi.enableException is true, then the internal 'Hwi_excHandlerMax'
722 * function is used. This exception handler saves the exception context
723 * then does a complete exception decode and dump to the console, then
724 * raises an Error. The exception context can be viewed within CCS
725 * in the ROV Hwi module's Exception view.
726 *
727 * If Hwi.enableException is false, then the internal 'Hwi_excHandlerMin'
728 * function is used. This exception handler saves the exception context
729 * then raises an Error. The exception context can be viewed within CCS
730 * in the ROV Hwi module's Exception view.
731 *
732 * If the user sets this parameter to their own function, then the user's
733 * function will be invoked with the following arguments:
734 *
735 * Void myExceptionHandler(UInt *excStack, UInt lr);
736 *
737 * Where 'excStack' is the address of the stack containing the
738 * register context at the time of the exception, and 'lr' is the
739 * link register value when the low-level-assembly-coded exception
740 * handler was vectored to.
741 *
742 * If this parameter is set to 'null', then an infinite while loop is
743 * entered when an exception occurs. This setting minimizes code and
744 * data footprint but provides no automatic exception decoding.
745 */
746 config ExcHandlerFuncPtr excHandlerFunc = excHandlerMax;
747
748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774
775 metaonly config UInt8 intAffinity[];
776
777 /*!
778 * Enable full exception decoding
779 *
780 * When this is enabled, the exception handler will fully
781 * decode an exception and dump the registers to the
782 * system console.
783 */
784 metaonly config Bool enableException = true;
785
786 /*!
787 * User Exception Context Buffer Address
788 *
789 * By default, when an exception occurs, an {@link #ExcContext}
790 * structure is allocated on the ISR stack and filled in within the
791 * exception handler.
792 *
793 * If {@link #excContextBuffer} is initialized by the user, the
794 * {@link #ExcContext} structure will be placed at that address instead.
795 *
796 * The buffer must be large enough to contain an {@link #ExcContext}
797 * structure.
798 */
799 metaonly config Ptr excContextBuffer;
800 metaonly config Ptr excContextBuffers[];
801
802 /*!
803 * User Exception Stack Buffer Address
804 *
805 * By default, when an exception occurs, a pointer to the base address
806 * of the stack being used by the thread causing the exception is placed
807 *
808 * If {@link #excStackBuffer} is initialized by the user, the
809 * stack contents of the thread causing the exception will be
810 * copied to that address instead.
811 *
812 * The buffer must be large enough to contain the largest task stack
813 * or ISR stack defined in the application.
814 */
815 metaonly config Ptr excStackBuffer;
816 metaonly config Ptr excStackBuffers[];
817
818
819 /*!
820 * User Exception hook function.
821 *
822 * Called just after the exception context has been initialized.
823 *
824 * This function will be run on the ISR stack.
825 *
826 * This function must run to completion.
827 *
828 * It is called without any Task or Swi scheduling protection
829 * and therefore can not call any functions that may cause a Swi or Task
830 * scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
831 */
832 config ExceptionHookFuncPtr excHookFunc = null;
833 config ExceptionHookFuncPtr excHookFuncs[];
834
835 /*!
836 * NVIC CCR register settings
837 *
838 * These setting are written to Hwi_nvic.CCR at startup time.
839 *
840 * See the Cortex M3 architecture reference manual for details
841 * on the meanings of these parameters.
842 */
843 metaonly config CCR nvicCCR = {
844 STKALIGN: 1,
845 BFHFNMIGN: 0,
846 DIV_0_TRP: 0,
847 UNALIGN_TRP: 0,
848 USERSETMPEND: 0,
849 NONEBASETHRDENA: 0
850 };
851
852 /*!
853 * The priority that BASEPRI is set to by Hwi_disable().
854 *
855 * All interrupts configured with equal or less priority (equal or
856 * higher number) than disablePriority are disabled by
857 * {@link #disable Hwi_disable}.
858 * Interrupts configured with higher priority (smaller number) than
859 * Hwi.disablePriority are non-maskable (ie zero-latency).
860 *
861 * The default setting is the second highest interrupt priority
862 * defined for the device (typically '0x20' for devices
863 * which support 8 priority values).
864 * This results in priority 0 (and all
865 * other values in the same priority group, ie 0x00 thru 0x1f)
866 * being the zero-latency, non-maskable interrupt priority.
867 * All other priorities are disabled with Hwi_disable().
868 */
869 config UInt disablePriority;
870
871 /*!
872 * The PRIGROUP setting. Default is 0.
873 *
874 * This value will be written to the PRIGROUP field
875 * within the NVIC's Application Interrupt and Reset Control
876 * Register (Hwi_nvic.AIRCR). It defines how the 8 bit priority
877 * values are interpreted by the hardware.
878 *
879 * Valid settings are 0-7.
880 *
881 * The default setting of 0 causes bits 7-1 of an interrupt's
882 * priority value to be used as pre-emption priority, while bit 0
883 * is used to determine which of two simultaneous interrupts with
884 * the same pre-emption priority will be serviced first.
885 *
886 * For most TI MCU devices, this means that each of the 8 supported
887 * priority values are unique pre-emption priorities and are not
888 * subdivided into priority groups.
889 */
890 config UInt priGroup = 0;
891
892
893
894 /*!
895 * ======== disable ========
896 * Disable all non zero-latency interrupts
897 *
898 * Hwi_disable disables all non zero-latency hardware interrupts and
899 * returns an
900 * opaque key indicating whether interrupts were globally enabled or
901 * disabled on entry to Hwi_disable().
902 * The actual value of the key is target/device specific and is meant
903 * to be passed to Hwi_restore().
904 *
905 * Call Hwi_disable before a portion of a function that needs
906 * to run without interruption. When critical processing is complete, call
907 * Hwi_restore or Hwi_enable to reenable hardware interrupts.
908 *
909 * Servicing of interrupts that occur while interrupts are disabled is
910 * postponed until interrupts are reenabled. However, if the same type
911 * of interrupt occurs several times while interrupts are disabled,
912 * the interrupt's function is executed only once when interrupts are
913 * reenabled.
914 *
915 * A context switch can occur when calling Hwi_enable or Hwi_restore if
916 * an enabled interrupt occurred while interrupts are disabled.
917 *
918 * Hwi_disable may be called from main(). However, since Hwi interrupts
919 * are already disabled in main(), such a call has no effect.
920 *
921 * @a(Implementation Note)
922 * In order to support zero latency interrupts, rather
923 * than setting PRIMASK (which would globally disable all NVIC
924 * interrupts), Hwi_disable() instead writes the value of
925 * {@link #disablePriority Hwi.disablePriority}
926 * to the BASEPRI register. In doing so, all interrupts of equal or
927 * lower priority than Hwi.disablePriority are disabled.
928 *
929 * @a(constraints)
930 * If a Task switching API such as
931 * {@link ti.sysbios.knl.Semaphore#pend Semaphore_pend()},
932 * {@link ti.sysbios.knl.Semaphore#post Semaphore_post()},
933 * {@link ti.sysbios.knl.Task#sleep Task_sleep()}, or
934 * {@link ti.sysbios.knl.Task#yield Task_yield()}
935 * is invoked which results in a context switch while
936 * interrupts are disabled, an embedded call to
937 * {@link #enable Hwi_enable} occurs
938 * on the way to the new thread context which unconditionally re-enables
939 * interrupts. Interrupts will remain enabled until a subsequent
940 * {@link #disable Hwi_disable}
941 * invocation.
942 *
943 * Swis always run with interrupts enabled.
944 * See {@link ti.sysbios.knl.Swi#post Swi_post()} for a discussion Swis and
945 * interrupts.
946 *
947 * @b(returns) opaque key for use by Hwi_restore()
948 */
949 @Macro
950 override UInt disable();
951
952 /*!
953 * ======== enable ========
954 */
955 @Macro
956 override UInt enable();
957
958 /*!
959 * ======== restore ========
960 */
961 @Macro
962 override Void restore(UInt key);
963
964 /*!
965 * @_nodoc
966 * ======== disableFxn ========
967 * function call implementation
968 */
969 UInt disableFxn();
970
971 /*!
972 * @_nodoc
973 * ======== enableFxn ========
974 * function call implementation
975 */
976 UInt enableFxn();
977
978 /*!
979 * @_nodoc
980 * ======== restoreFxn ========
981 * function call implementation
982 */
983 Void restoreFxn(UInt key);
984
985 /*!
986 * ======== inUseMeta ========
987 * @_nodoc
988 * Check for Hwi already in use.
989 * For internal SYS/BIOS use only.
990 * Should be called prior to any internal Hwi.create().
991 *
992 * @param(intNum) interrupt number
993 */
994 metaonly Bool inUseMeta(UInt intNum);
995
996 /*!
997 * ======== plug ========
998 * Plug a non dispatched interrupt vector with an ISR address.
999 *
1000 * Used internally by Hwi_create() and Hwi_construct().
1001 *
1002 * This API is provided for external use primarily to allow users
1003 * to plug the NMI vector (interrupt #2) at runtime.
1004 *
1005 * @a(Note)
1006 * Interrupt vectors plugged using Hwi_plug() are NOT managed by
1007 * the Hwi interrupt dispatcher. Consequently, it is not safe to
1008 * call SYS/BIOS APIs from within these ISRs.
1009 *
1010 * @param(intNum) interrupt number
1011 * @param(fxn) pointer to ISR function
1012 */
1013 Void plug(UInt intNum, Void *fxn);
1014
1015 /*!
1016 * ======== getHandle ========
1017 * Returns Hwi_handle associated with intNum
1018 *
1019 * @param(intNum) interrupt number
1020 */
1021 Handle getHandle(UInt intNum);
1022
1023 /*!
1024 * ======== setPriority ========
1025 * Set an interrupt's relative priority.
1026 *
1027 * Valid priorities are 0 - 255. 0 is highest priority.
1028 *
1029 * @a(WARNING)
1030 * Setting the priority of a dispatched Hwi to a value higher
1031 * than {@link #disablePriority Hwi.disablePriority} will make
1032 * it become non-maskable by {@link #disable Hwi_disable()}.
1033 * The behavior of your application after that will be
1034 * unpredictable and will likely yield catastrophic results!
1035 *
1036 * @param(intNum) ID of interrupt
1037 * @param(priority) priority
1038 */
1039 Void setPriority(UInt intNum, UInt priority);
1040
1041 /*!
1042 * ======== excSetBuffers ========
1043 * Set the exception context and stack buffer pointers
1044 *
1045 * @param(excContextBuffer) Address to place ExcContext
1046 * @param(excStackBuffer) Address to place ExcStack
1047 */
1048 Void excSetBuffers(Ptr excContextBuffer, Ptr excStackBuffer);
1049
1050 /*!
1051 * @_nodoc
1052 * ======== initNVIC ========
1053 * initialize everything but leave ints disabled
1054 */
1055 Void initNVIC();
1056
1057 /*!
1058 * @_nodoc
1059 * ======== initStacks ========
1060 * set up M3 split stacks
1061 */
1062 Void initStacks(Ptr hwiStack);
1063
1064 /*!
1065 * @_nodoc
1066 * ======== flushVnvic ========
1067 * Reconfigure a dispatched interrupt.
1068 *
1069 * Called by the internal function "Hwi_updateNvic()".
1070 *
1071 * This is a public API because it is also called by "Core_hwiFunc()".
1072 */
1073 Void flushVnvic();
1074
1075 instance:
1076
1077 /*!
1078 * Interrupt priority.
1079 * The default is 255 which is the lowest priority.
1080 *
1081 * Priority 0 is the highest priority and by default is
1082 * reserved for zero latency interrupts
1083 * (see {@link #disablePriority}).
1084 *
1085 * Valid priorities values are device dependent and their
1086 * nesting behaviors depend on the {@link #priGroup} setting.
1087 *
1088 * See the Cortex M3 architecture reference manual for details
1089 * on the meanings of these parameters.
1090 */
1091 override config Int priority = 255;
1092
1093 /*!
1094 * Interrupt Masking Option. Only MaskingOption_LOWER is supported.
1095 *
1096 * The NVIC interrupt controller is designed for priority based
1097 * interrupts. No support is provided for anything but
1098 * Hwi.MaskingOption_LOWER.
1099 */
1100 override config IHwi.MaskingOption maskSetting = IHwi.MaskingOption_LOWER;
1101
1102 /*!
1103 * Use the interrupt dispatcher with this interrupt. Default is true.
1104 *
1105 * If set to false, the interrupt dispatcher is NOT used. Instead,
1106 * the configured Hwi function address is placed directly in the
1107 * vector table, which results in the dispatcher being bypassed.
1108 *
1109 * @a(Warning)
1110 * Interrupts configured to bupass the dispatcher are not allowed
1111 * to call ANY SYS/BIOS APIs that effect thread scheduling. Examples
1112 * of API that should no be invoked are:
1113 *
1114 * @p(dlist)
1115 * - Swi_post(),
1116 * - Semaphore_post(),
1117 * - Event_post(),
1118 * - Task_yield()
1119 * @p
1120 *
1121 * Additionally, although the signature for a non-dispatched interrupt
1122 * function is the same as that for a dispatched interrupt
1123 * (see {@link #FuncPtr}), no argument is actually passed
1124 * to the non-dispatched ISR handler.
1125 */
1126 config Bool useDispatcher = true;
1127
1128 /*!
1129 * ======== reconfig ========
1130 * Reconfigure a dispatched interrupt.
1131 */
1132 Void reconfig(FuncPtr fxn, const Params *params);
1133
1134 internal:
1135
1136 /*!
1137 * If Hwi.dispatchTableSize is initialized by the user then
1138 * Hwi.numSparseInterrupts is set to the value of Hwi.dispatchTableSize
1139 *
1140 * If Hwi.dispatchTableSize is NOT set by the user, the normal
1141 * intNum-indexed Hwi dispatchTable mechanism is used by
1142 * the dispatcher to find the corresponding Hwi object.
1143 *
1144 * If Hwi.dispatchTableSize is set by the user, then a
1145 * RAM-based fixed sized interrupt jump table is generated
1146 * that contains a repeating pattern of the following 3 word
1147 * assembly code snippets:
1148 *
1149 * hwiX: ldr r3, hwiObjectX
1150 * ldr pc, ti_sysbios_family_arm_m3_Hwi_dispatch__I
1151 * hwiObjectX: .word 0
1152 * hwiY: ldr r3, hwiObjectY
1153 * ldr pc, ti_sysbios_family_arm_m3_Hwi_dispatch__I
1154 * hwiObjectY: .word 0
1155 * ...
1156 *
1157 * Each dispatched interrupt vector is then initialized to point
1158 * to one of these tuples, and the address of the corresponding Hwi
1159 * object is written into the hwiObjectX field.
1160 *
1161 * The low level assembly code in Hwi_dispatch__I preserves the
1162 * value of r3 when it calls Hwi_dispatchC(), which results in
1163 * the Hwi object being passed as the arg3.
1164 *
1165 * Depending on the boolean value of Hwi_numSparseInterrupts, the
1166 * dispatcher either uses the value passed in arg3 as the
1167 * Hwi object, or uses intNum to index into the standard
1168 * dispatchTable to fetch the Hwi object.
1169 */
1170 config UInt numSparseInterrupts = 0;
1171
1172 1173 1174 1175
1176 metaonly config Bool isTiva = false;
1177
1178 1179 1180 1181 1182 1183 1184 1185 1186
1187 metaonly config Bool enableWA1_1 = false;
1188
1189 1190 1191 1192 1193 1194
1195 config UInt (*swiDisable)();
1196 config Void (*swiRestoreHwi)(UInt);
1197 config UInt (*taskDisable)();
1198 config Void (*taskRestoreHwi)(UInt);
1199
1200
1201 config UInt32 ccr;
1202
1203 /*!
1204 * const array to hold all HookSet objects.
1205 */
1206 config HookSet hooks[length] = [];
1207
1208 1209 1210 1211
1212 Int postInit(Object *hwi, Error.Block *eb);
1213
1214 /*!
1215 * ======== updateNvic ========
1216 * Internal SMP function to cause the virtual NVIC to be flushed to the
1217 * actual NVIC.
1218 *
1219 * This function is called by the various user APIs that manipulate
1220 * individual NVIC register bits
1221 * (ie Hwi_enable/disable/restore/clearInterrupt())
1222 *
1223 * If the current core is the owner of "intNum", flushVnvic() is called
1224 * immediately.
1225 *
1226 * Otherwise an intercore interrupt is generated to force the other core
1227 * to perform the flushVnvic().
1228 *
1229 */
1230 Void updateNvic(UInt intNum);
1231
1232 /*!
1233 * ======== excHandlerAsm ========
1234 * asm code exception handler
1235 */
1236 Void excHandlerAsm();
1237
1238 /*!
1239 * ======== excHandler ========
1240 * exception Handler routes to
1241 * either min, max, or spin exception handler
1242 */
1243 Void excHandler(UInt *excStack, UInt lr);
1244
1245 /*!
1246 * ======== excHandlerMin ========
1247 * Minimal Exception Handler
1248 */
1249 Void excHandlerMin(UInt *excStack, UInt lr);
1250
1251 /*!
1252 * ======== excHandlerMax ========
1253 * Full Featured Exception Handler
1254 */
1255 Void excHandlerMax(UInt *excStack, UInt lr);
1256
1257 /*!
1258 * ======== excFillContext ========
1259 */
1260 Void excFillContext(UInt *excStack);
1261
1262 /*!
1263 * ======== excNmi ========
1264 */
1265 Void excNmi(UInt *excStack);
1266
1267 /*!
1268 * ======== excHardFault ========
1269 */
1270 Void excHardFault(UInt *excStack);
1271
1272 /*!
1273 * ======== excMemFault ========
1274 */
1275 Void excMemFault(UInt *excStack);
1276
1277 /*!
1278 * ======== excBusFault ========
1279 */
1280 Void excBusFault(UInt *excStack);
1281
1282 /*!
1283 * ======== excUsageFault ========
1284 */
1285 Void excUsageFault(UInt *excStack);
1286
1287 /*!
1288 * ======== excSvCall ========
1289 */
1290 Void excSvCall(UInt *excStack);
1291
1292 /*!
1293 * ======== excDebugMon ========
1294 */
1295 Void excDebugMon(UInt *excStack);
1296
1297 /*!
1298 * ======== excReserved ========
1299 */
1300 Void excReserved(UInt *excStack, UInt excNum);
1301
1302 /*!
1303 * ======== excNoIsr ========
1304 */
1305 Void excNoIsr(UInt *excStack, UInt excNum);
1306
1307 /*!
1308 * ======== excDumpRegs ========
1309 */
1310 Void excDumpRegs(UInt lr);
1311
1312 /*!
1313 * ======== pendSV ========
1314 * Used by dispatcher
1315 */
1316 Void pendSV();
1317
1318 /*! Hwi vector function type definition. */
1319 typedef Void (*HandlerFuncPtr)(Handle, UInt);
1320
1321
1322 Void dispatch();
1323
1324 1325 1326 1327 1328 1329
1330 Void romInitNVIC();
1331
1332 1333 1334 1335
1336 UInt dispatchC(Irp irp, UInt32 dummy1, UInt32 dummy2, Object *hwi);
1337
1338
1339 Void doSwiRestore(UInt tskKey);
1340
1341
1342 Void doTaskRestore(UInt tskKey);
1343
1344 /*! Meta World Only Hwi Configuration Object. */
1345 metaonly struct InterruptObj {
1346 String name;
1347 Bool used;
1348 Bool useDispatcher;
1349 UInt priority;
1350 FuncPtr fxn;
1351 Handle hwi;
1352 };
1353
1354 /*!
1355 * Meta-only array of interrupt objects.
1356 * This meta-only array of Hwi config objects is initialized
1357 * in Hwi.xs:module$meta$init().
1358 */
1359 metaonly config InterruptObj interrupt[];
1360
1361 struct Instance_State {
1362 UArg arg;
1363 FuncPtr fxn;
1364 Irp irp;
1365
1366 UInt8 priority;
1367 Int16 intNum;
1368
1369
1370 Ptr hookEnv[];
1371 };
1372
1373 struct Module_State {
1374 Char *taskSP;
1375
1376 Bool excActive[];
1377 ExcContext *excContext[];
1378 Ptr excStack[];
1379 Ptr isrStack;
1380 Ptr isrStackBase;
1381 Ptr isrStackSize;
1382 Ptr vectorTableBase;
1383 UInt swiTaskKeys;
1384 Ptr dispatchTable;
1385 volatile Bool vnvicFlushRequired;
1386
1387 UInt8 intAffinity[];
1388 UInt32 intAffinityMasks[][];
1389 };
1390 }