1    /*
     2     * Copyright (c) 2014, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    /*
    33     *  ======== Power.xdc ========
    34     *
    35     *
    36     */
    37    
    38    package ti.sysbios.family.arm.ducati.omap4430;
    39    
    40    import ti.sysbios.family.arm.ducati.GateDualCore;
    41    
    42    /*!
    43     *  ======== Power ========
    44     *  Power support for Ducati on OMAP4430.
    45     */
    46    @DirectCall
    47    module Power
    48    {
    49        /*! Suspend function hook. */
    50        typedef Void (*SuspendFuncHookPtr)();
    51    
    52        /*! Suspend arguments structure. */
    53        struct SuspendArgs {
    54            Bool pmMasterCore;     /*! Master core for suspend/resume? */
    55            Bool rendezvousResume; /*! Rendezvous before resume? */
    56            Int dmaChannel;        /*! SDMA channel for L2 RAM save; -1=CPU copy */
    57            UInt intMask31_0;     /*! Mask of interrupts (31-0) able to wake WFI */
    58            UInt intMask63_32;    /*! Mask of interrupts (63-32) able to wake WFI */
    59            UInt intMask79_64;    /*! Mask of interrupts (79-64) able to wake WFI */
    60        };
    61    
    62        /*! Physical address of L2 RAM */
    63        const Ptr L2RAM = 0x55020000;
    64    
    65        /*! Base address of SDMA registers */
    66        config Ptr sdmaRegs = 0x4A056000;
    67    
    68        /*! Rendezvous Gate index */
    69        config UInt rendezvousGateIndex = 1;
    70    
    71        /*! Idle the CPU when threads blocked waiting for an interrupt? */
    72        config Bool idle = false;
    73    
    74        /*! Segment to load Power's shared reset code and data */
    75        metaonly config String loadSegment = "EXT_SHARED_RAM";
    76    
    77        /*! 
    78         *  Pre-suspend function hooks.  Called on Core 0 (only), before beginning 
    79         *  context save.
    80         *
    81         *  To configure a function to run as Pre suspend hook, add a statement
    82         *  like the following to the application configuration script:
    83         * 
    84         *  @p(code)
    85         *  Power.preSuspendHooks.$add("&myHook");
    86         *  @p
    87         *
    88         *  Multiple hook functions can be added following this same pattern.
    89         */
    90        config SuspendFuncHookPtr preSuspendHooks[length] = [];
    91    
    92        /*! 
    93         *  Post-suspend function hooks.  Called on Core 0 (only), after context
    94         *  restore, immediately before returning from suspend.
    95         *
    96         *  To configure a function to run as Post suspend hook, add a statement
    97         *  like the following to the application configuration script:
    98         * 
    99         *  @p(code)
   100         *  Power.postSuspendHooks.$add("&myHook");
   101         *  @p
   102         *
   103         *  Multiple hook functions can be added following this same pattern.
   104         */
   105        config SuspendFuncHookPtr postSuspendHooks[length] = [];
   106    
   107        /*!
   108         *  ======== idleCPU ========
   109         *  Function used to automatically idle the CPU in the Idle loop.
   110         *
   111         *  When the 'idle' configuration parameter is set, this function will
   112         *  be added to the list of Idle loop functions.  When called from the
   113         *  Idle loop, it will invoke the wait for interrupt (WFI) instruction,
   114         *  to idle the CPU until the next interrupt occurs.
   115         */
   116        Void idleCPU();
   117    
   118        /*!
   119         *  ======== suspend ========
   120         *  Function used for suspend/resume of the M3 cores.
   121         *
   122         *  Precondition and usage constraints: 
   123         *   
   124         *  1) Before this function is called the application must disable all 
   125         *     interrupts that are not desired to wake the CPU from WFI while 
   126         *     waiting for the core domain to go off.  
   127         *
   128         *  2) For those interrupts that are desired to wake the CPU from WFI (for
   129         *     example, the mailbox interrupt), these interrupts cannot be generated
   130         *     until the Power_suspend API has reached the point of executing WFI.
   131         *     If the interrupts happen early, while this API is saving context,
   132         *     the resulting context may be stale, and the application may not 
   133         *     resume correctly.  Two global flags (one for each M3 core) are 
   134         *     assert immediately before invoking WFI; the wakeup interrupts 
   135         *     should not be asserted until these flags are asserted (non-zero):
   136         *          ti_sysbios_family_arm_ducati_omap4430_readyIdleCore0
   137         *          ti_sysbios_family_arm_ducati_omap4430_readyIdleCore1
   138         */
   139        UInt suspend(SuspendArgs * args);
   140    
   141    internal:
   142    
   143        struct Struct8 {
   144            UInt32 a0;
   145            UInt32 a1;
   146            UInt32 a2;
   147            UInt32 a3;
   148            UInt32 a4;
   149            UInt32 a5;
   150            UInt32 a6;
   151            UInt32 a7;
   152        }
   153    
   154        struct Struct10 {
   155            UInt32 a0;
   156            UInt32 a1;
   157            UInt32 a2;
   158            UInt32 a3;
   159            UInt32 a4;
   160            UInt32 a5;
   161            UInt32 a6;
   162            UInt32 a7;
   163            UInt32 a8;
   164            UInt32 a9;
   165        }
   166    
   167        struct TablePIDS {
   168            UInt32 PID1;
   169            UInt32 PID2;
   170        }
   171    
   172        struct IPRxRegs {
   173            UInt32 IPR0;
   174            UInt32 IPR1;
   175            UInt32 IPR2;
   176            UInt32 IPR3;
   177            UInt32 IPR4;
   178            UInt32 IPR5;
   179            UInt32 IPR6;
   180            UInt32 IPR7;
   181            UInt32 IPR8;
   182            UInt32 IPR9;
   183            UInt32 IPR10;
   184            UInt32 IPR11;
   185            UInt32 IPR12;
   186            UInt32 IPR13;
   187            UInt32 IPR14;
   188            UInt32 IPR15;
   189        }
   190    
   191        struct CfgRegs {
   192            UInt32 VTOR;
   193            UInt32 AIRCR;
   194            UInt32 SCR;
   195            UInt32 CCR;
   196            UInt32 SHPR0;
   197            UInt32 SHPR4;
   198            UInt32 SHPR8;
   199            UInt32 SHCSR;
   200        }
   201    
   202        struct NVICContext {
   203            UInt32 AUXCTRL;
   204            UInt32 STCSR;
   205            UInt32 STRVR;
   206            UInt32 ISER0;
   207            UInt32 ISER1;
   208            IPRxRegs iprRegs;
   209            CfgRegs cfgRegs;
   210        }
   211    
   212        struct ContextAMMU {
   213            UInt32 largeAddr[4];
   214            UInt32 largeXlteAddr[4];
   215            UInt32 largePolicy[4];
   216            UInt32 medAddr[2];
   217            UInt32 medXlteAddr[2];
   218            UInt32 medPolicy[2];
   219            Struct10 smallAddr;
   220            Struct10 smallXlteAddr;
   221            Struct10 smallPolicy;
   222            UInt32 mmuConfig;
   223        }
   224    
   225        struct ContextCTM {
   226            UInt32 CNTL;
   227            UInt32 STMCNTL;
   228            UInt32 STMMSTID;
   229            UInt32 STMINTVL;
   230            UInt32 STMSEL0;
   231            UInt32 TINTVLR0;
   232            UInt32 TINTVLR1;
   233            UInt32 GNBL0;
   234            Struct8 control;
   235        }
   236    
   237        struct CpuRegs {
   238            UInt32 R4;
   239            UInt32 R5;
   240            UInt32 R6;
   241            UInt32 R7;
   242            UInt32 R8;
   243            UInt32 R9;
   244            UInt32 R10;
   245            UInt32 R11;
   246            UInt32 LR;
   247            UInt32 CONTROL;
   248            UInt32 BASEPRI;
   249            UInt32 MSP;
   250            UInt32 pSP;
   251        }
   252    
   253        struct PrivateContext {
   254            CpuRegs privateCPU;
   255            NVICContext privateNVIC;
   256            TablePIDS privatePIDS;
   257        } 
   258    
   259        struct UnicacheConfig {
   260            UInt32 L1_CONFIG;
   261            UInt32 L1_OCP;
   262        }
   263    
   264        struct SubsystemContext {
   265            UnicacheConfig cacheConfig;
   266            ContextAMMU ammuConfig;
   267            ContextCTM ctmConfig;
   268        }
   269    
   270        struct DucatiContext {
   271            PrivateContext masterContext;
   272            PrivateContext slaveContext;
   273            SubsystemContext ssContext;
   274        }
   275    
   276        struct SdmaRegs {
   277            volatile UInt32 CCR;
   278            UInt32 CLNK;
   279            UInt32 CICR;
   280            UInt32 CSR;
   281            UInt32 CSDP;
   282            UInt32 CEN;
   283            UInt32 CFN;
   284            UInt32 CSSA;
   285            UInt32 CDSA;
   286            UInt32 CSEI;
   287            UInt32 CSFI;
   288            UInt32 CDEI;
   289            UInt32 CDFI;
   290        }
   291    
   292        /*! Rendezvous Gate handle */
   293        config GateDualCore.Handle rendezvousGate;
   294    
   295        /*!
   296         *  ======== resetFxn ========
   297         *  Function used for resume upon reset of M3 cores.
   298         */
   299        Void resetFxn();
   300    
   301        /*!
   302         *  ======== saveCpuRegs ========
   303         *  Function used to save parent-preserved CPU register context, assert
   304         *  ready to idle flag, and invoke WFI.
   305         */
   306        UInt32 saveCpuRegs(Ptr saveAddress, Ptr readyFlag);
   307    
   308    }
   309