1    /*
     2     * Copyright (c) 2012, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    /*
    33     *  ======== TimestampProvider.xdc ========
    34     */
    35    
    36    package ti.sysbios.family.arm.ducati;
    37    
    38    import xdc.rov.ViewInfo;
    39    
    40    /*!
    41     *  ======== TimestampProvider ========
    42     *  Ducati Cortex M3 TimestampProvider delegate for use 
    43     *  with {@link xdc.runtime.Timestamp}
    44     *
    45     *  The timestamp counters used in Ducati are CTM counters 2,3,4,5.
    46     *  Each core uses two counters in chained mode to achieve 64 bits.
    47     *  Core 0 uses counters 2,3.
    48     *  Core 1 uses counters 4,5.
    49     *  Which ever core is started first will start both sets of counters 
    50     *  synchronously so that both cores effectively share a common timestamp.
    51     *  By default, the CTM counters are clocked at 2 times the CPU clock.
    52     *
    53     *
    54     *  @p(html)
    55     *  <h3> Calling Context </h3>
    56     *  <table border="1" cellpadding="3">
    57     *    <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
    58     *
    59     *    <tr><th> Function                 </th><th>  Hwi   </th><th>  Swi   </th><th>  Task  </th><th>  Main**  </th><th>  Startup***  </th></tr>
    60     *    <!--                                                                                                                 -->
    61     *    <tr><td> {@link #get32}           </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   N    </td></tr>
    62     *    <tr><td> {@link #get64}           </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   N    </td></tr>
    63     *    <tr><td> {@link #getFreq}         </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   Y    </td><td>   N    </td></tr>
    64     *
    65     *  </table>
    66     *  @p
    67     */
    68    
    69    @ModuleStartup          /* To get Clock Timer Handle */
    70    
    71    module TimestampProvider inherits ti.sysbios.interfaces.ITimestamp
    72    {
    73    
    74        /*! @_nodoc */
    75        metaonly struct ModuleView {
    76            String      timestamp;
    77        }
    78    
    79        @Facet
    80        metaonly config ViewInfo.Instance rovViewInfo = 
    81            ViewInfo.create({
    82                viewMap: [
    83                [
    84                    'Module',
    85                    {
    86                        type: ViewInfo.MODULE,
    87                        viewInitFxn: 'viewInitModule',
    88                        structName: 'ModuleView'
    89                    }
    90                ],
    91                ]
    92            });
    93    
    94        /*! 
    95         * Counter Input Select. The default value of 0 selects the 
    96         * 2x CPU clock as the clock source for the timestamp counters.
    97         *
    98         * See Table 28-22 of the OMAP4430 TRM for details of the
    99         * various events that can be counted.
   100         * 1 Cache locks
   101         * 2 Cache line replacements
   102         * 3 Cache evictions
   103         * 4 Cache maintenance operations (slave 0)
   104         * 5 Cache maintenance operations (slave 1)
   105         * 6 Cache maintenance operations (slave 2)
   106         * 7 Cache maintenance operations (slave 3)
   107         * 8 Cache OCP access (slave 0)
   108         * 9 Cache OCP access (slave 1)
   109         * 10 Cache OCP access (slave 2)
   110         * 11 Cache OCP access (slave 3)
   111         * 12 Cacheable access (slave 0)
   112         * 13 Cacheable access (slave 1)
   113         * 14 Cacheable access (slave 2)
   114         * 15 Cacheable access (slave 3)
   115         * 16 Cache bank conflicts (slave 0)
   116         * 17 Cache bank conflicts (slave 1)
   117         * 18 Cache bank conflicts (slave 2)
   118         * 19 Cache bank conflicts (slave 3)
   119         * 20 Cache allocations
   120         * 21 Cache write buffer accesses (slave 0)
   121         * 22 Cache write buffer accesses (slave 1)
   122         * 23 Cache write buffer accesses (slave 2)
   123         * 24 Cache write buffer accesses (slave 3)
   124         * 25 Cache line fills (slave 0)
   125         * 26 Cache line fills (slave 1)
   126         * 27 Cache line fills (slave 2)
   127         * 28 Cache line fills (slave 3)
   128         * 29 Cache write fills (slave 0)
   129         * 30 Cache write fills (slave 1)
   130         * 31 Cache write fills (slave 2)
   131         * 32 Cache write fills (slave 3)
   132         * 33 Cache read fills (slave 0)
   133         * 34 Cache read fills (slave 1)
   134         * 35 Cache read fills (slave 2)
   135         * 36 Cache read fills (slave 3)
   136         * 37 Cache misses (slave 0)
   137         * 38 Cache misses (slave 1)
   138         * 39 Cache misses (slave 2)
   139         * 40 Cache misses (slave 3)
   140         * 41 Cache hits (slave 0)
   141         * 42 Cache hits (slave 1)
   142         * 43 Cache hits (slave 2)
   143         * 44 Cache hits (slave 3)
   144         * 45 Cortex-M3 ISS CTL deep sleep
   145         * 46 Cortex-M3 ISS CTL sleep
   146         * 47 Cortex-M3 RTOS deep sleep
   147         * 48 Cortex-M3 RTOS sleep
   148         */
   149        config UInt8 inpsel = 0;
   150    }