1 /*
2 * Copyright (c) 2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /*
33 * ======== Core.xdc ========
34 *
35 */
36
37 import xdc.runtime.Error;
38 import ti.sysbios.family.arm.ducati.GateSmp;
39
40 /*!
41 * ======== Core ========
42 * Core Identification Module.
43 *
44 * The Core module is used to define which core within a dual core
45 * "Ducati" subsystem an application is being built for.
46 *
47 * At runtime, a comparison is made between the configured Core.id
48 * and the value of PID0 (at address 0xe00fffe0). If they do not
49 * agree, an Error is raised.
50 *
51 * Use of this module has the side effect of configuring default
52 * interrupt vector table placements for Core 0 and Core 1 if
53 * they haven't already been specified by the
54 * {@link ti.sysbios.family.arm.m3.Hwi#vectorTableAddress Hwi.vectorTableAddress}
55 * config parameter.
56 *
57 * Core 0's default vector table placement is at 0x400.
58 *
59 * Core 1's default vector table placement is at 0x800.
60 */
61
62 @ModuleStartup /* to configure static timers */
63
64 module Core inherits ti.sysbios.interfaces.ICore
65 {
66 /*! Hwi scheduler lock bits */
67 const UInt HWI_SCHEDULER_LOCK = 0x0001;
68
69 /*! Swi scheduler lock bits */
70 const UInt SWI_SCHEDULER_LOCK = 0x0002;
71
72 /*! Task scheduler lock bits */
73 const UInt TASK_SCHEDULER_LOCK = 0x0004;
74
75 /*!
76 * Error raised if Core.id does not match the contents
77 * of PID0 (at 0xE00FFFE0).
78 */
79 config Error.Id E_mismatchedIds = {
80 msg: "E_mismatchedIds: Core_Id: %d does not match hardware core Id: %d"
81 };
82
83 override config UInt numCores = 2;
84
85 /*!
86 * Non SMP Ducati Core ID, default is Core 0
87 *
88 * Used for making static decisions based on Core ID
89 */
90 config UInt id = 0;
91
92 /*!
93 * Core's IPU ID, default is IPU 1
94 *
95 * Used to identify core belongs to which IPU sub-system.
96 * This field has only 2 possible valid values, 1 or 2.
97 */
98 config UInt ipuId = 1;
99
100 /*!
101 * Core 1's interrupt stack size, default is Program.stack.
102 */
103 config SizeT core1HwiStackSize;
104
105 @Macro
106 override UInt hwiDisable();
107
108 @Macro
109 override UInt hwiEnable();
110
111 @Macro
112 override Void hwiRestore(UInt key);
113
114 /*!
115 * ======== syncExits ========
116 * synchronize exits for all cores
117 *
118 * If flag set to true, then the first core that exits
119 * (calls BIOS_exit), interrupts the other core and
120 * waits for it to exit.
121 */
122 config Bool syncExits = true;
123
124 /*!
125 * ======== getIpuId ========
126 * return the current core's IPU id
127 */
128 UInt getIpuId();
129
130 /*!
131 * @_nodoc
132 * ======== getCore1HwiStackBase ========
133 */
134 Ptr getCore1HwiStackBase();
135
136 internal:
137
138 config GateSmp.Handle gate;
139
140 config Bool initStackFlag = true;
141
142 /*
143 * ======== hwiFunc ========
144 *
145 * Hwi func attached to Core.interruptCore()
146 */
147 Void hwiFunc(UArg arg);
148
149 /*
150 * ======== startCore1 ========
151 *
152 * Installed as Task.startHookFunc
153 * Called by Core 0
154 */
155 Void startCore1();
156
157 /*
158 * ======== core1Startup ========
159 *
160 * Core 1's first function
161 * begins at the same time
162 */
163 Void core1Startup();
164
165 /*!
166 * ======== atexit ========
167 * atexit() func used to signal the other core to halt
168 */
169 Void atexit(Int arg);
170
171 struct Module_State {
172 volatile Bool exitFlag; /* if true in Core_hwiFunc(), then jump to exit */
173 Bool gateEntered[2];
174 UInt schedulerInts[2];
175 Char core1HwiStack[];
176 };
177 }
178