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C6x Register Usage

Arm9 DSP/BIOS Register Usage

This document provides a table describing the various Arm9 targets register conventions in terms of preservation across multi-threaded context switching and preconditions.

Overview

In a multi-threaded application using DSP/BIOS, it is necessary to know which registers can or cannot be modified. Furthermore, users need to understand which registers need to be saved/restored across a function call or an interrupt.

The following definitions describe the various possible register handling behaviors:

• Scratch register. These registers are saved/restored by the Hwi dispatcher with temporary register bit masks.
• Preserved register. These registers are saved/restored during a Task context switch.
• Initialized register. These registers are set to a particular value during Hwi processing and restored to their incoming value upon exiting from the interrupt routine.
• Read-Only register. These registers may be read but must not be modified.
• Global register. These registers are shared across all threads in the system. To make a temporary change, save the register, make the change, and then restore it.
• Other. These registers do not fit into one of the categories above.

Register Conventions

Table 1 Register and Status Bit Handling

Register	Status Bit	Register or Status Bit Name	Type	Notes
R0-R3, R12		General purpose registers	Scratch
R4-R11		General purpose registers	Preserved
R13 (SP)		Stack pointer	Initialized	Hwi dispatcher sets to Hwi stack before calling ISR
R14 (LR)		Link Register	Preserved
PSR		Program Status Register
	N,Z,C,V	Condition Codes	Preserved
	Q	Overflow	Preserved
	GE[3:0]	Condition Codes	Preserved
	E	Endian bit	Preserved	Untouched
	A	Imprecise Abort Disable	Preserved	Untouched
	I	IRQ Disable	Global	Hwi_enable/disable/restore operate on this bit
	F	FIQ Disable	Preserved	?The FIQ bit is preserved and untouched by BIOS
	M[4:0]	Mode bits	Other	BIOS sets the mode bits to System Mode (0b11111) during startup and prior to invoking a Hwi thread.
	T	Thumb	Global	BIOS fully supports Arm/Thumb inter-working.
	J	Jazelle	Preserved	Untouched
R13_svc		Supervisor mode R13	Other	? Untouched
R14_svc		Supervisor mode R14	Other	? Untouched
SPSR_svc		Supervisor mode SPSR	Other	? Untouched
R13_abt		Abort mode R13	Other	? Untouched
R14_abt		Abort mode R14	Other	? Untouched
SPSR_abt		Abort mode SPSR	Other	? Untouched
R13_und		Undefined mode R13	Other	? Untouched
R14_und		Undefined mode R14	Other	? Untouched
SPSR_und		Undefined mode SPSR	Other	? Untouched
R13_irq		Interrupt mode R13	Initialized	? BIOS sets to top of IRQ stack buffer (Hwi.irqStack)
R14_irq		Interrupt mode R14	Other	? During ISR, points to interrupt return address
SPSR_iq		Interrupt mode SPSR	Other	? Untouched
R8_fiq-R12_fiq		FIQ banked registers	Other	Untouched
R13_fiq		FIQ mode R13	Initialized	? BIOS sets to top of FIQ stack buffer (Hwi.fiqStack)
R14_fiq		FIQ mode R14	Other	? Untouched
SPSR_fiq		FIQ mode SPSR	Other	? Untouched

Notes:

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