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37
38 package ti.sysbios.family.arm.da830;
39
40 import xdc.runtime.Assert;
41
42 /*!
43 * ======== TimestampProvider ========
44 * Provides.da830 specific timestamp APIs to xdc.runtime.Timestamp
45 *
46 * Uses the iceCrusher Benchmark counters.
47 * @p(html)
48 * <h3> Calling Context </h3>
49 * <table border="1" cellpadding="3">
50 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
51 *
52 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
53 * <!-- -->
54 * <tr><td> {@link #get32} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
55 * <tr><td> {@link #get64} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
56 * <tr><td> {@link #getFreq} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
57 * <tr><td colspan="6"> Definitions: <br />
58 * <ul>
59 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
60 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
61 * <li> <b>Task</b>: API is callable from a Task thread. </li>
62 * <li> <b>Main</b>: API is callable during any of these phases: </li>
63 * <ul>
64 * <li> In your module startup after this module is started (e.g. TimestampProvider_Module_startupDone() returns TRUE). </li>
65 * <li> During xdc.runtime.Startup.lastFxns. </li>
66 * <li> During main().</li>
67 * <li> During BIOS.startupFxns.</li>
68 * </ul>
69 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
70 * <ul>
71 * <li> During xdc.runtime.Startup.firstFxns.</li>
72 * <li> In your module startup before this module is started (e.g. TimestampProvider_Module_startupDone() returns FALSE).</li>
73 * </ul>
74 * </ul>
75 * </td></tr>
76 *
77 *
78 * </table>
79 * @p
80 */
81
82 @ModuleStartup
83
84 module TimestampProvider inherits ti.sysbios.interfaces.ITimestamp
85 {
86
87 /*!
88 * CountType
89 *
90 * @c(CountType_CYCLES)
91 * Timestamp is in cycles.
92 *
93 * @c(CountType_INSTRUCTIONS)
94 * Timestamp is in instructions.
95 */
96
97 enum CountType {
98 CountType_CYCLES, /*! count cycles */
99 CountType_INSTRUCTIONS /*! count instructions */
100 };
101
102 struct IceCrusherRegs {
103 UInt32 VER; /*! 0x00 Revision */
104 UInt32 DBGCFG; /*! 0x04 Debug Config */
105 UInt32 DBGCNTL; /*! 0x08 Debug Control & Status */
106 UInt32 RES_0C; /*! 0x0C Reserved */
107 UInt32 TRIGCNTL; /*! 0x10 Trigger Control */
108 UInt32 RSTCNTL; /*! 0x14 Reset Control */
109 UInt32 THRDIDCLM; /*! 0x18 Thread ID Claim */
110 UInt32 THRDID; /*! 0x1c Thread ID */
111 UInt32 INTCNTL; /*! 0x20 Interrupt Control */
112 UInt32 ETMCNTL; /*! 0x24 ETM Control */
113 UInt32 ETMPID; /*! 0x28 ETM Process ID */
114 UInt32 TEST; /*! 0x2C Test */
115 UInt32 SWBRKCTL; /*! 0x30 Software Breakpoint Control */
116 UInt32 SWBRKVAL; /*! 0x34 Software Breakpoint Value */
117 UInt32 RES_38; /*! 0x38 Reserved */
118 UInt32 RES_3C; /*! 0x3C Reserved */
119 UInt32 BCNT0CTRL; /*! 0x40 Benchmark Counter 0 Control */
120 UInt32 BCNT0; /*! 0x44 Benchmark Counter 0 */
121 UInt32 RES_48; /*! 0x48 Reserved */
122 UInt32 RES_4C; /*! 0x4C Reserved */
123 UInt32 BCNT1CTRL; /*! 0x50 Benchmark Counter 1 Control */
124 UInt32 BCNT1; /*! 0x54 Benchmark Counter 1 */
125 UInt32 RES_58[10]; /*! 0x58 - 0x7C Reserved */
126 UInt32 HWBRK0CTL; /*! 0x80 Hardware Breakpoint 0 Control */
127 UInt32 HWBRK0ADR; /*! 0x84 Hardware Breakpoint 0 Address */
128 UInt32 HWBRK0ADRMASK; /*! 0x88 Hardware Breakpoint 0 Address Mask */
129 UInt32 RES_8C; /*! 0x8C Reserved */
130 UInt32 HWBRK1CTL; /*! 0x90 Hardware Breakpoint 1 Control */
131 UInt32 HWBRK1ADR; /*! 0x94 Hardware Breakpoint 1 Address */
132 UInt32 HWBRK1ADRMASK; /*! 0x98 Hardware Breakpoint 1 Address Mask */
133 UInt32 RES_9C; /*! 0x9C Reserved */
134 UInt32 HWBRK2CTL; /*! 0xA0 Hardware Breakpoint 2 Control */
135 UInt32 HWBRK2ADR; /*! 0xA4 Hardware Breakpoint 2 Address */
136 UInt32 HWBRK2ADRMASK; /*! 0xA8 Hardware Breakpoint 2 Address Mask */
137 UInt32 RES_AC; /*! 0xAC Reserved */
138 UInt32 HWBRK3CTL; /*! 0xB0 Hardware Breakpoint 3 Control */
139 UInt32 HWBRK3ADR; /*! 0xB4 Hardware Breakpoint 3 Address */
140 UInt32 HWBRK3ADRMASK; /*! 0xB8 Hardware Breakpoint 3 Address Mask */
141 UInt32 RES_BC[14]; /*! 0xBC - 0xF0 Reserved */
142 UInt32 OS_LOCKSTS; /*! 0xF4 OS Lock Status */
143 UInt32 OS_LOCK; /*! 0xF8 OS Lock */
144 UInt32 DCON; /*! 0xFC DCON Register */
145 }
146
147 extern volatile IceCrusherRegs iceRegs;
148
149 /*! @_nodoc */
150 @XmlDtd
151 metaonly struct Module_View {
152 UInt32 upper32Bits;
153 };
154
155 /*! Assert when configured benchmark counter is owned by CCS */
156 config Assert.Id A_counterInUse = {
157 msg: "A_counterInUse: Benchmark counter already claimed."
158 };
159
160 /*! Assert if interrupt control register is owned by CCS */
161 config Assert.Id A_intControlInUse = {
162 msg: "A_intCOntrolInUse: iceCrusher Int Control Register already claimed."
163 };
164
165 /*! ICECrusher Benchmark Counter id. 0 or 1. Default is 1 */
166 config UInt benchmarkCounterId = 1;
167
168 /*!
169 * Timestamp count type. Default is CYCLES.
170 * CountType_INSTRUCTIONS only supported on benchmarkCounterId 1!!!
171 */
172 config CountType countType = CountType_CYCLES;
173
174 internal:
175
176 177 178
179 Void overflowHandler(UArg arg);
180
181 182 183
184 Void releaseCounters();
185
186 struct Module_State {
187 UInt32 upper32Bits;
188 Hwi.Handle hwi;
189 }
190 }