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38
39 package ti.platforms.evmTI813X;
40
41 /*!
42 * ======== Platform ========
43 * Platform support for the evmTI813X
44 *
45 * This module implements xdc.platform.IPlatform and defines configuration
46 * parameters that correspond to this platform's Cpu's, Board's, etc.
47 *
48 * The configuration parameters are initialized in this package's
49 * configuration script (package.cfg) and "bound" to the TCOM object
50 * model. Once they are part of the model, these parameters are
51 * queried by a program's configuration script.
52 *
53 * This particular platform has 3 CPU's, a host GPP, and 2 M3's.
54 */
55 metaonly module Platform inherits xdc.platform.IPlatform
56 {
57 /*!
58 * ======== BOARD ========
59 * This platform's board attributes
60 */
61 readonly config xdc.platform.IPlatform.Board BOARD = {
62 id: "0",
63 boardName: "evmTI813X",
64 boardFamily: "evmTI813X",
65 boardRevision: null
66 };
67
68
69 readonly config xdc.platform.IExeContext.Cpu DSS = {
70 id: "0",
71 clockRate: 200.0,
72 catalogName: "ti.catalog.arm.cortexm3",
73 deviceName: "TMS320TI813X",
74 revision: "1.0"
75 };
76
77
78 readonly config xdc.platform.IExeContext.Cpu GPP = {
79 id: "1",
80 clockRate: 600.0,
81 catalogName: "ti.catalog.arm.cortexa8",
82 deviceName: "TMS320TI813X",
83 revision: "1.0"
84 };
85
86 instance:
87
88 override readonly config xdc.platform.IPlatform.Memory
89 externalMemoryMap[string] = [
90 ["DDR3_HOST", {
91 comment: "DDR3 Memory reserved for use by the A8",
92 name: "DDR3_HOST",
93 base: 0x80000000,
94 len: 0x0D000000
95 }],
96 ["DDR3_SR1", {
97 comment: "DDR3 Memory reserved for use by SharedRegion 1",
98 name: "DDR3_SR1",
99 base: 0x8D000000,
100 len: 0x00C00000
101 }],
102 ["DDR3_HDVPSS", {
103 comment: "DDR3 Memory reserved for use by HDVPSS",
104 name: "DDR3_HDVPSS",
105 base: 0x8DC00000,
106 len: 0x00200000
107 }],
108 ["DDR3_V4L2", {
109 comment: "DDR3 Memory reserved for use by V4L2",
110 name: "DDR3_V4L2",
111 base: 0x8DE00000,
112 len: 0x00200000
113 }],
114 ["DDR3_SR0", {
115 comment: "DDR3 Memory reserved for use by SharedRegion 0",
116 name: "DDR3_SR0",
117 base: 0x8E000000,
118 len: 0x01000000
119 }],
120 ["DDR3_M3", {
121 comment: "DDR3 Memory reserved for use by the M3 core",
122 name: "DDR3_M3",
123 base: 0x8F000000,
124 len: 0x01000000
125 }],
126 ];
127
128 };