1 /*
2 * Copyright (c) 2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== Platform.xdc ========
35 * Platform support for evmC6A8149
36 *
37 */
38
39 package ti.platforms.evmC6A8149;
40
41 /*!
42 * ======== Platform ========
43 * Platform support for the evmC6A8149
44 *
45 * This module implements xdc.platform.IPlatform and defines configuration
46 * parameters that correspond to this platform's Cpu's, Board's, etc.
47 *
48 * The configuration parameters are initialized in this package's
49 * configuration script (package.cfg) and "bound" to the TCOM object
50 * model. Once they are part of the model, these parameters are
51 * queried by a program's configuration script.
52 *
53 * This particular platform has 4 CPU's, a host GPP, 2 M3's, and a
54 * C674 DSP.
55 */
56 metaonly module Platform inherits xdc.platform.IPlatform
57 {
58 readonly config xdc.platform.IPlatform.Board BOARD = {
59 id: "0",
60 boardName: "evmC6A8149",
61 boardFamily: "evmC6A8149",
62 boardRevision: null
63 };
64
65 /* C674 GEM */
66 readonly config xdc.platform.IExeContext.Cpu GEM = {
67 id: "0",
68 clockRate: 500.0,
69 catalogName: "ti.catalog.c6000",
70 deviceName: "TMS320C6A8149",
71 revision: ""
72 };
73
74
75 /* EVE - ARP32 */
76 readonly config xdc.platform.IExeContext.Cpu EVE = {
77 id: "1",
78 clockRate: 225.0,
79 catalogName: "ti.catalog.arp32",
80 deviceName: "TMS320C6A8149",
81 revision: ""
82 };
83
84 /* M3 Subsystem */
85 readonly config xdc.platform.IExeContext.Cpu DSS = {
86 id: "2",
87 clockRate: 200.0,
88 catalogName: "ti.catalog.arm.cortexm3",
89 deviceName: "TMS320C6A8149",
90 revision: "1.0"
91 };
92
93 /* GPP */
94 readonly config xdc.platform.IExeContext.Cpu GPP = {
95 id: "3",
96 clockRate: 600.0, /* Typically set by the HLOS */
97 catalogName: "ti.catalog.arm.cortexa8",
98 deviceName: "TMS320C6A8149",
99 revision: "1.0"
100 };
101
102 instance:
103
104 override readonly config xdc.platform.IPlatform.Memory
105 externalMemoryMap[string] = [
106 ["DDR3_HOST", {
107 comment: "DDR3 Memory reserved for use by the A8",
108 name: "DDR3_HOST",
109 base: 0x80000000,
110 len: 0x0B000000 /* 176 MB */
111 }],
112 ["DDR3_DSP", {
113 comment: "DDR3 Memory reserved for use by the C674",
114 name: "DDR3_DSP",
115 base: 0x8B000000,
116 len: 0x02000000 /* 32 MB */
117 }],
118 ["DDR3_SR1", {
119 comment: "DDR3 Memory reserved for use by SharedRegion 1",
120 name: "DDR3_SR1",
121 base: 0x8D000000,
122 len: 0x00C00000 /* 12 MB */
123 }],
124 ["DDR3_HDVPSS", {
125 comment: "DDR3 Memory reserved for use by HDVPSS",
126 name: "DDR3_HDVPSS",
127 base: 0x8DC00000,
128 len: 0x00200000 /* 2 MB */
129 }],
130 ["DDR3_V4L2", {
131 comment: "DDR3 Memory reserved for use by V4L2",
132 name: "DDR3_V4L2",
133 base: 0x8DE00000,
134 len: 0x00200000 /* 2 MB */
135 }],
136 ["DDR3_SR0", {
137 comment: "DDR3 Memory reserved for use by SharedRegion 0",
138 name: "DDR3_SR0",
139 base: 0x8E000000,
140 len: 0x01000000 /* 16 MB */
141 }],
142 ["DDR3_M3", {
143 comment: "DDR3 Memory reserved for use by the M3 core",
144 name: "DDR3_M3",
145 base: 0x8F000000,
146 len: 0x01000000 /* 16 MB */
147 }],
148 ["DDR3_EVEVECS", {
149 comment: "DDR3 Memory reserved for use by the EVE int vectors",
150 name: "DDR3_EVEVECS",
151 base: 0x90000000,
152 len: 0x00000100 /* 256 Bytes */
153 }],
154 ["DDR3_EVE", {
155 comment: "DDR3 Memory reserved for use by the EVE",
156 name: "DDR3_EVE",
157 base: 0x90000100,
158 len: 0x00FFFF00 /* 16MB - 256 Bytes */
159 }],
160 ];
161
162 /*
163 * ======== l1PMode ========
164 * Define the amount of L1P RAM used for L1 Program Cache.
165 *
166 * Check the device documentation for valid values.
167 */
168 config String l1PMode = "32k";
169
170 /*
171 * ======== l1DMode ========
172 * Define the amount of L1D RAM used for L1 Data Cache.
173 *
174 * Check the device documentation for valid values.
175 */
176 config String l1DMode = "32k";
177
178 /*
179 * ======== l2Mode ========
180 * Define the amount of L2 RAM used for L2 Cache.
181 *
182 * Check the device documentation for valid values.
183 */
184 config String l2Mode = "0k";
185 };