The Boot module supports boot initialization for the C28 Soprano cores.
A special boot init function is created based on the configuration
settings for this module. This function is hooked into the
xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
to cinit processing).
The code to support the boot module is placed in a separate section
named
".text:.bootCodeSection" to allow placement of this section in
the linker .cmd file if necessary. This section is a subsection of the
".text" section so this code will be placed into the .text section unless
explicitly placed, either through
Program.sectMap or through a linker
command file.
metaonly enum Boot.FractMult |
|
System PLL Fractional Multiplier (SPLLFMULT) value
values of type Boot.FractMult
const Boot.Fract_0;
// Fractional multiplier is 0
const Boot.Fract_25;
// Fractional multiplier is 0.25
const Boot.Fract_50;
// Fractional multiplier is 0.5
const Boot.Fract_75;
// Fractional multiplier is 0.75
metaonly enum Boot.OscClk |
|
Oscillator Clock Source Select Bit for OSCCLK
values of type Boot.OscClk
const Boot.OscClk_INTOSC2;
// internal oscillator 2 (default on reset)
const Boot.OscClk_XTAL;
// external oscillator
const Boot.OscClk_INTOSC1;
// internal oscillator 1
const Boot.OscClk_RESERVED;
// reserved (default to INTOSC1)
metaonly struct Boot.ModuleView |
|
var obj = new Boot.ModuleView;
obj.configureClocks = Bool ...
obj.OSCCLK = UInt ...
obj.SPLLIMULT = UInt ...
obj.SPLLFMULT = String ...
obj.SYSCLKDIVSEL = String ...
obj.bootCPU2 = Bool ...
config Boot.configureClocks // module-wide |
|
Clock configuration flag, default is false
Boot.configureClocks = Bool false;
DETAILS
Set to true to configure the PLL and system subsystem clock
dividers.
C SYNOPSIS
metaonly config Boot.OSCCLK // module-wide |
|
OSCCLK input frequency to PLL, in MHz
DETAILS
This is the frequency of the oscillator clock (OSCCLK) input to the
PLL. The default internal oscillator is 10 Mhz.
metaonly config Boot.OSCCLKSRCSEL // module-wide |
|
Oscillator Clock source select bit for OSCCLK
DETAILS
The default on reset is INTOSC2
metaonly config Boot.SPLLFMULT // module-wide |
|
System PLL Fractional Multiplier (SPLLFMULT) value
metaonly config Boot.SPLLIMULT // module-wide |
|
System PLL Integer Multiplier (SPLLIMULT) value
metaonly config Boot.SYSCLKDIVSEL // module-wide |
|
System Clock Divider Select (SYSCLKDIVSEL) value
Boot.SYSCLKDIVSEL = UInt 2;
metaonly config Boot.bootCPU2 // module-wide |
|
Initiate booting of the CPU2 processor. Default is false
Boot.bootCPU2 = Bool false;
DETAILS
Set to true to enable CPU1 to initiate boot of CPU2.
If enabled, this will occur after the optional clock configuration
step, enabled by
configureClocks.
metaonly config Boot.bootFromFlash // module-wide |
|
Boot from Flash flag. Default is true
Boot.bootFromFlash = Bool true;
DETAILS
Set to true to enable booting CPU1 from Flash.
metaonly config Boot.configSharedRAMs // module-wide |
|
Configure Shared RAM regions before booting the C28 processor.
Default is true
Boot.configSharedRAMs = Bool true;
DETAILS
Set to true to enable Shared RAM regions S0-S7, to set the
owner of each region and the write access permissions for the onwer.
metaonly config Boot.configureFlashController // module-wide |
|
Flash controller configuration flag, default is true
Boot.configureFlashController = Bool true;
DETAILS
Set to true to enable the configuration of the Flash controller
wait states, program and data cache.
metaonly config Boot.configureFlashWaitStates // module-wide |
|
Flash controller wait states configuration flag, default is true
Boot.configureFlashWaitStates = Bool true;
DETAILS
Set to true to configure the Flash controller wait states. The number
of wait states is computed based upon the CPU frequency.
metaonly config Boot.disableWatchdog // module-wide |
|
Watchdog disable flag, default is false
Boot.disableWatchdog = Bool false;
DETAILS
Set to true to disable the watchdog timer.
metaonly config Boot.enableFlashDataCache // module-wide |
|
Flash controller data cache enable flag, default is true
Boot.enableFlashDataCache = Bool true;
DETAILS
Set to true to enable the Flash controller's data cache.
metaonly config Boot.enableFlashProgramCache // module-wide |
|
Flash controller program cache enable flag, default is true
Boot.enableFlashProgramCache = Bool true;
DETAILS
Set to true to enable the Flash controller's program cache.
metaonly config Boot.limpAbortFunction // module-wide |
|
Function to be called when Limp mode is detected
Boot.limpAbortFunction = Fxn undefined;
DETAILS
This function is called when the Boot module is about to configure
the PLL, but finds the device operating in Limp mode (i.e., the mode
when a missing OSCCLK input has been detected).
If this function is not specified by the application, a default
function will be used, which spins in an infinite loop.
metaonly config Boot.loadSegment // module-wide |
|
Specifies where to load the flash function (include the 'PAGE' number)
Boot.loadSegment = String undefined;
DETAILS
If 'configureFlashWaitStates' is true, then this parameter
determines where the ".ti_catalog_c2800_initF2837x_flashfuncs"
section gets loaded.
metaonly config Boot.rovViewInfo // module-wide |
|
metaonly config Boot.runSegment // module-wide |
|
Specifies where to run the flash function (include the 'PAGE' number)
Boot.runSegment = String undefined;
DETAILS
If 'configureFlashWaitStates' is true then this parameter
determines where the ".ti_catalog_c2800_initF2837x_flashfuncs"
section gets executed at runtime.
metaonly config Boot.sharedMemoryOwnerMask // module-wide |
|
Shared RAM owner select mask
Boot.sharedMemoryOwnerMask = Bits32 0;
DETAILS
This parameter is used for writing the GSxMSEL register.
By default, each value of each shared RAM select bit is '0'.
This means the CPU1 is the owner and has write access.
Setting a '1' in any bit position makes CPU2 the owner of that
shared RAM segment.