1    /*
     2     * Copyright (c) 2013, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     * */
    32    
    33    /*
    34     *  ======== Boot.xdc ========
    35     */
    36    
    37    package ti.catalog.arm.cortexm4.tiva.ce;
    38    
    39    import xdc.rov.ViewInfo;
    40    import xdc.runtime.Assert;
    41    
    42    /*!
    43     *  ======== Boot ========
    44     *  Stellaris M3 Boot Support.
    45     *
    46     *  The Boot module supports boot initialization for the Stellaris M3 devices.
    47     *  A special boot init function is created based on the configuration
    48     *  settings for this module.  This function is hooked into the
    49     *  xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
    50     *  to cinit processing).
    51     *
    52     *  The code to support the boot module is placed in a separate section
    53     *  named `".text:.bootCodeSection"` to allow placement of this section in
    54     *  the linker .cmd file if necessary. This section is a subsection of the
    55     *  `".text"` section so this code will be placed into the .text section unless
    56     *  explicitly placed, either through
    57     *  `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
    58     *  command file.
    59     */
    60    @Template("./Boot.xdt")
    61    module Boot
    62    {
    63        metaonly struct ModuleView {
    64            Bool    configureClock;
    65            Bool    sysClockDivEnable;
    66            String  sysClockDiv;
    67            Bool    pwmClockDivEnable;
    68            String  pwmClockDiv;
    69            String  xtal;
    70            String  oscSrc;
    71            Bool    pllBypass;
    72            Bool    pllOutEnable;
    73            Bool    ioscDisable;
    74            Bool    moscDisable;
    75        }
    76    
    77        @Facet
    78        metaonly config ViewInfo.Instance rovViewInfo =
    79            ViewInfo.create({
    80                viewMap: [
    81                [
    82                    'Module',
    83                    {
    84                        type: ViewInfo.MODULE,
    85                        viewInitFxn: 'viewInitModule',
    86                        structName: 'ModuleView'
    87                    }
    88                ],
    89                ]
    90            });
    91    
    92    
    93        metaonly enum SysDiv {
    94            SYSDIV_1     = 0x07800000,  /*! CPU clock is osc/pll / 1 */
    95            SYSDIV_2     = 0x00C00000,  /*! CPU clock is osc/pll / 2 */
    96            SYSDIV_3     = 0x01400000,  /*! CPU clock is osc/pll / 3 */
    97            SYSDIV_4     = 0x01C00000,  /*! CPU clock is osc/pll / 4 */
    98            SYSDIV_5     = 0x02400000,  /*! CPU clock is osc/pll / 5 */
    99            SYSDIV_6     = 0x02C00000,  /*! CPU clock is osc/pll / 6 */
   100            SYSDIV_7     = 0x03400000,  /*! CPU clock is osc/pll / 7 */
   101            SYSDIV_8     = 0x03C00000,  /*! CPU clock is osc/pll / 8 */
   102            SYSDIV_9     = 0x04400000,  /*! CPU clock is osc/pll / 9 */
   103            SYSDIV_10    = 0x04C00000,  /*! CPU clock is osc/pll / 10 */
   104            SYSDIV_11    = 0x05400000,  /*! CPU clock is osc/pll / 11 */
   105            SYSDIV_12    = 0x05C00000,  /*! CPU clock is osc/pll / 12 */
   106            SYSDIV_13    = 0x06400000,  /*! CPU clock is osc/pll / 13 */
   107            SYSDIV_14    = 0x06C00000,  /*! CPU clock is osc/pll / 14 */
   108            SYSDIV_15    = 0x07400000,  /*! CPU clock is osc/pll / 15 */
   109            SYSDIV_16    = 0x07C00000,  /*! CPU clock is osc/pll / 16 */
   110            SYSDIV_17    = 0x88400000,  /*! CPU clock is osc/pll / 17 */
   111            SYSDIV_18    = 0x88C00000,  /*! CPU clock is osc/pll / 18 */
   112            SYSDIV_19    = 0x89400000,  /*! CPU clock is osc/pll / 19 */
   113            SYSDIV_20    = 0x89C00000,  /*! CPU clock is osc/pll / 20 */
   114            SYSDIV_21    = 0x8A400000,  /*! CPU clock is osc/pll / 21 */
   115            SYSDIV_22    = 0x8AC00000,  /*! CPU clock is osc/pll / 22 */
   116            SYSDIV_23    = 0x8B400000,  /*! CPU clock is osc/pll / 23 */
   117            SYSDIV_24    = 0x8BC00000,  /*! CPU clock is osc/pll / 24 */
   118            SYSDIV_25    = 0x8C400000,  /*! CPU clock is osc/pll / 25 */
   119            SYSDIV_26    = 0x8CC00000,  /*! CPU clock is osc/pll / 26 */
   120            SYSDIV_27    = 0x8D400000,  /*! CPU clock is osc/pll / 27 */
   121            SYSDIV_28    = 0x8DC00000,  /*! CPU clock is osc/pll / 28 */
   122            SYSDIV_29    = 0x8E400000,  /*! CPU clock is osc/pll / 29 */
   123            SYSDIV_30    = 0x8EC00000,  /*! CPU clock is osc/pll / 30 */
   124            SYSDIV_31    = 0x8F400000,  /*! CPU clock is osc/pll / 31 */
   125            SYSDIV_32    = 0x8FC00000,  /*! CPU clock is osc/pll / 32 */
   126            SYSDIV_33    = 0x90400000,  /*! CPU clock is osc/pll / 33 */
   127            SYSDIV_34    = 0x90C00000,  /*! CPU clock is osc/pll / 34 */
   128            SYSDIV_35    = 0x91400000,  /*! CPU clock is osc/pll / 35 */
   129            SYSDIV_36    = 0x91C00000,  /*! CPU clock is osc/pll / 36 */
   130            SYSDIV_37    = 0x92400000,  /*! CPU clock is osc/pll / 37 */
   131            SYSDIV_38    = 0x92C00000,  /*! CPU clock is osc/pll / 38 */
   132            SYSDIV_39    = 0x93400000,  /*! CPU clock is osc/pll / 39 */
   133            SYSDIV_40    = 0x93C00000,  /*! CPU clock is osc/pll / 40 */
   134            SYSDIV_41    = 0x94400000,  /*! CPU clock is osc/pll / 41 */
   135            SYSDIV_42    = 0x94C00000,  /*! CPU clock is osc/pll / 42 */
   136            SYSDIV_43    = 0x95400000,  /*! CPU clock is osc/pll / 43 */
   137            SYSDIV_44    = 0x95C00000,  /*! CPU clock is osc/pll / 44 */
   138            SYSDIV_45    = 0x96400000,  /*! CPU clock is osc/pll / 45 */
   139            SYSDIV_46    = 0x96C00000,  /*! CPU clock is osc/pll / 46 */
   140            SYSDIV_47    = 0x97400000,  /*! CPU clock is osc/pll / 47 */
   141            SYSDIV_48    = 0x97C00000,  /*! CPU clock is osc/pll / 48 */
   142            SYSDIV_49    = 0x98400000,  /*! CPU clock is osc/pll / 49 */
   143            SYSDIV_50    = 0x98C00000,  /*! CPU clock is osc/pll / 50 */
   144            SYSDIV_51    = 0x99400000,  /*! CPU clock is osc/pll / 51 */
   145            SYSDIV_52    = 0x99C00000,  /*! CPU clock is osc/pll / 52 */
   146            SYSDIV_53    = 0x9A400000,  /*! CPU clock is osc/pll / 53 */
   147            SYSDIV_54    = 0x9AC00000,  /*! CPU clock is osc/pll / 54 */
   148            SYSDIV_55    = 0x9B400000,  /*! CPU clock is osc/pll / 55 */
   149            SYSDIV_56    = 0x9BC00000,  /*! CPU clock is osc/pll / 56 */
   150            SYSDIV_57    = 0x9C400000,  /*! CPU clock is osc/pll / 57 */
   151            SYSDIV_58    = 0x9CC00000,  /*! CPU clock is osc/pll / 58 */
   152            SYSDIV_59    = 0x9D400000,  /*! CPU clock is osc/pll / 59 */
   153            SYSDIV_60    = 0x9DC00000,  /*! CPU clock is osc/pll / 60 */
   154            SYSDIV_61    = 0x9E400000,  /*! CPU clock is osc/pll / 61 */
   155            SYSDIV_62    = 0x9EC00000,  /*! CPU clock is osc/pll / 62 */
   156            SYSDIV_63    = 0x9F400000,  /*! CPU clock is osc/pll / 63 */
   157            SYSDIV_64    = 0x9FC00000,  /*! CPU clock is osc/pll / 64 */
   158            SYSDIV_2_5   = 0xC1000000,  /*! CPU clock is osc/pll / 2.5 */
   159            SYSDIV_3_5   = 0xC1800000,  /*! CPU clock is osc/pll / 3.5 */
   160            SYSDIV_4_5   = 0xC2000000,  /*! CPU clock is osc/pll / 4.5 */
   161            SYSDIV_5_5   = 0xC2800000,  /*! CPU clock is osc/pll / 5.5 */
   162            SYSDIV_6_5   = 0xC3000000,  /*! CPU clock is osc/pll / 6.5 */
   163            SYSDIV_7_5   = 0xC3800000,  /*! CPU clock is osc/pll / 7.5 */
   164            SYSDIV_8_5   = 0xC4000000,  /*! CPU clock is osc/pll / 8.5 */
   165            SYSDIV_9_5   = 0xC4800000,  /*! CPU clock is osc/pll / 9.5 */
   166            SYSDIV_10_5  = 0xC5000000,  /*! CPU clock is osc/pll / 10.5 */
   167            SYSDIV_11_5  = 0xC5800000,  /*! CPU clock is osc/pll / 11.5 */
   168            SYSDIV_12_5  = 0xC6000000,  /*! CPU clock is osc/pll / 12.5 */
   169            SYSDIV_13_5  = 0xC6800000,  /*! CPU clock is osc/pll / 13.5 */
   170            SYSDIV_14_5  = 0xC7000000,  /*! CPU clock is osc/pll / 14.5 */
   171            SYSDIV_15_5  = 0xC7800000,  /*! CPU clock is osc/pll / 15.5 */
   172            SYSDIV_16_5  = 0xC8000000,  /*! CPU clock is osc/pll / 16.5 */
   173            SYSDIV_17_5  = 0xC8800000,  /*! CPU clock is osc/pll / 17.5 */
   174            SYSDIV_18_5  = 0xC9000000,  /*! CPU clock is osc/pll / 18.5 */
   175            SYSDIV_19_5  = 0xC9800000,  /*! CPU clock is osc/pll / 19.5 */
   176            SYSDIV_20_5  = 0xCA000000,  /*! CPU clock is osc/pll / 20.5 */
   177            SYSDIV_21_5  = 0xCA800000,  /*! CPU clock is osc/pll / 21.5 */
   178            SYSDIV_22_5  = 0xCB000000,  /*! CPU clock is osc/pll / 22.5 */
   179            SYSDIV_23_5  = 0xCB800000,  /*! CPU clock is osc/pll / 23.5 */
   180            SYSDIV_24_5  = 0xCC000000,  /*! CPU clock is osc/pll / 24.5 */
   181            SYSDIV_25_5  = 0xCC800000,  /*! CPU clock is osc/pll / 25.5 */
   182            SYSDIV_26_5  = 0xCD000000,  /*! CPU clock is osc/pll / 26.5 */
   183            SYSDIV_27_5  = 0xCD800000,  /*! CPU clock is osc/pll / 27.5 */
   184            SYSDIV_28_5  = 0xCE000000,  /*! CPU clock is osc/pll / 28.5 */
   185            SYSDIV_29_5  = 0xCE800000,  /*! CPU clock is osc/pll / 29.5 */
   186            SYSDIV_30_5  = 0xCF000000,  /*! CPU clock is osc/pll / 30.5 */
   187            SYSDIV_31_5  = 0xCF800000,  /*! CPU clock is osc/pll / 31.5 */
   188            SYSDIV_32_5  = 0xD0000000,  /*! CPU clock is osc/pll / 32.5 */
   189            SYSDIV_33_5  = 0xD0800000,  /*! CPU clock is osc/pll / 33.5 */
   190            SYSDIV_34_5  = 0xD1000000,  /*! CPU clock is osc/pll / 34.5 */
   191            SYSDIV_35_5  = 0xD1800000,  /*! CPU clock is osc/pll / 35.5 */
   192            SYSDIV_36_5  = 0xD2000000,  /*! CPU clock is osc/pll / 36.5 */
   193            SYSDIV_37_5  = 0xD2800000,  /*! CPU clock is osc/pll / 37.5 */
   194            SYSDIV_38_5  = 0xD3000000,  /*! CPU clock is osc/pll / 38.5 */
   195            SYSDIV_39_5  = 0xD3800000,  /*! CPU clock is osc/pll / 39.5 */
   196            SYSDIV_40_5  = 0xD4000000,  /*! CPU clock is osc/pll / 40.5 */
   197            SYSDIV_41_5  = 0xD4800000,  /*! CPU clock is osc/pll / 41.5 */
   198            SYSDIV_42_5  = 0xD5000000,  /*! CPU clock is osc/pll / 42.5 */
   199            SYSDIV_43_5  = 0xD5800000,  /*! CPU clock is osc/pll / 43.5 */
   200            SYSDIV_44_5  = 0xD6000000,  /*! CPU clock is osc/pll / 44.5 */
   201            SYSDIV_45_5  = 0xD6800000,  /*! CPU clock is osc/pll / 45.5 */
   202            SYSDIV_46_5  = 0xD7000000,  /*! CPU clock is osc/pll / 46.5 */
   203            SYSDIV_47_5  = 0xD7800000,  /*! CPU clock is osc/pll / 47.5 */
   204            SYSDIV_48_5  = 0xD8000000,  /*! CPU clock is osc/pll / 48.5 */
   205            SYSDIV_49_5  = 0xD8800000,  /*! CPU clock is osc/pll / 49.5 */
   206            SYSDIV_50_5  = 0xD9000000,  /*! CPU clock is osc/pll / 50.5 */
   207            SYSDIV_51_5  = 0xD9800000,  /*! CPU clock is osc/pll / 51.5 */
   208            SYSDIV_52_5  = 0xDA000000,  /*! CPU clock is osc/pll / 52.5 */
   209            SYSDIV_53_5  = 0xDA800000,  /*! CPU clock is osc/pll / 53.5 */
   210            SYSDIV_54_5  = 0xDB000000,  /*! CPU clock is osc/pll / 54.5 */
   211            SYSDIV_55_5  = 0xDB800000,  /*! CPU clock is osc/pll / 55.5 */
   212            SYSDIV_56_5  = 0xDC000000,  /*! CPU clock is osc/pll / 56.5 */
   213            SYSDIV_57_5  = 0xDC800000,  /*! CPU clock is osc/pll / 57.5 */
   214            SYSDIV_58_5  = 0xDD000000,  /*! CPU clock is osc/pll / 58.5 */
   215            SYSDIV_59_5  = 0xDD800000,  /*! CPU clock is osc/pll / 59.5 */
   216            SYSDIV_60_5  = 0xDE000000,  /*! CPU clock is osc/pll / 60.5 */
   217            SYSDIV_61_5  = 0xDE800000,  /*! CPU clock is osc/pll / 61.5 */
   218            SYSDIV_62_5  = 0xDF000000,  /*! CPU clock is osc/pll / 62.5 */
   219            SYSDIV_63_5  = 0xDF800000   /*! CPU clock is osc/pll / 63.5 */
   220        }
   221    
   222        metaonly enum PwmDiv {
   223            PWMDIV_1     = 0x00000000,  /*! PWM clock /1 */
   224            PWMDIV_2     = 0x00100000,  /*! PWM clock /2 */
   225            PWMDIV_4     = 0x00120000,  /*! PWM clock /4 */
   226            PWMDIV_8     = 0x00140000,  /*! PWM clock /8 */
   227            PWMDIV_16    = 0x00160000,  /*! PWM clock /16 */
   228            PWMDIV_32    = 0x00180000,  /*! PWM clock /32 */
   229            PWMDIV_64    = 0x001A0000   /*! PWM clock /64 */
   230        }
   231    
   232        metaonly enum XtalFreq {
   233            XTAL_1MHZ    = 0x00000000,  /*! 1.0 MHz */
   234            XTAL_1_84MHZ = 0x00000040,  /*! 1.8432 MHz */
   235            XTAL_2MHZ    = 0x00000080,  /*! 2.0 MHz */
   236            XTAL_2_45MHZ = 0x000000C0,  /*! 2.4576 MHz */
   237            XTAL_3_57MHZ = 0x00000100,  /*! 3.579545 MHz */
   238            XTAL_3_68MHZ = 0x00000140,  /*! 3.6864 MHz */
   239            XTAL_4MHZ    = 0x00000180,  /*! 4.0 MHz */
   240            XTAL_4_09MHZ = 0x000001C0,  /*! 4.096 MHz */
   241            XTAL_4_91MHZ = 0x00000200,  /*! 4.9152 MHz */
   242            XTAL_5MHZ    = 0x00000240,  /*! 5.0 MHz */
   243            XTAL_5_12MHZ = 0x00000280,  /*! 5.12 MHz */
   244            XTAL_6MHZ    = 0x000002C0,  /*! 6.0 MHz */
   245            XTAL_6_14MHZ = 0x00000300,  /*! 6.144 MHz */
   246            XTAL_7_37MHZ = 0x00000340,  /*! 7.3728 MHz */
   247            XTAL_8MHZ    = 0x00000380,  /*! 8.0 MHz */
   248            XTAL_8_19MHZ = 0x000003C0,  /*! 8.192 MHz */
   249            XTAL_10MHZ   = 0x00000400,  /*! 10.0 MHz (USB) */
   250            XTAL_12MHZ   = 0x00000440,  /*! 12.0 MHz (USB) */
   251            XTAL_12_2MHZ = 0x00000480,  /*! 12.288 MHz */
   252            XTAL_13_5MHZ = 0x000004C0,  /*! 13.56 MHz */
   253            XTAL_14_3MHZ = 0x00000500,  /*! 14.31818 MHz */
   254            XTAL_16MHZ   = 0x00000540,  /*! 16.0 MHz (USB) */
   255            XTAL_16_3MHZ = 0x00000580,  /*! 16.384 MHz */
   256            XTAL_18MHZ   = 0x000005C0,  /*! 18.0 MHz */
   257            XTAL_20MHZ   = 0x00000600,  /*! 20.0 MHz */
   258            XTAL_24MHZ   = 0x00000640,  /*! 24.0 MHz */
   259            XTAL_25MHZ   = 0x00000680   /*! 25.0 MHz */
   260        }
   261    
   262        metaonly enum OscSrc {
   263            OSCSRC_MAIN     = 0x00000000,  /*! Main oscillator */
   264            OSCSRC_INT      = 0x00000010,  /*! Internal oscillator */
   265            OSCSRC_INT4     = 0x00000020,  /*! Internal oscillator / 4 */
   266            OSCSRC_INT30    = 0x00000030,  /*! Internal 30 KHz oscillator */
   267            OSCSRC_EXT4_19  = 0x80000028,  /*! External 4.19 MHz */
   268            OSCSRC_EXT32    = 0x80000038   /*! External 32 KHz */
   269        }
   270    
   271        /* The LDO setting is not supported on TIVA devices */
   272        metaonly enum LdoOut {
   273            LDOPCTL_2_55V    = 0x0000001F,  /* LDO output of 2.55V */
   274            LDOPCTL_2_60V    = 0x0000001E,  /* LDO output of 2.60V */
   275            LDOPCTL_2_65V    = 0x0000001D,  /* LDO output of 2.65V */
   276            LDOPCTL_2_70V    = 0x0000001C,  /* LDO output of 2.70V */
   277            LDOPCTL_2_75V    = 0x0000001B,  /* LDO output of 2.75V */
   278            LDOPCTL_2_25V    = 0x00000005,  /* LDO output of 2.25V */
   279            LDOPCTL_2_30V    = 0x00000004,  /* LDO output of 2.30V */
   280            LDOPCTL_2_35V    = 0x00000003,  /* LDO output of 2.35V */
   281            LDOPCTL_2_40V    = 0x00000002,  /* LDO output of 2.40V */
   282            LDOPCTL_2_45V    = 0x00000001,  /* LDO output of 2.45V */
   283            LDOPCTL_2_50V    = 0x00000000   /* LDO output of 2.50V */
   284        }
   285    
   286        metaonly enum VcoFreq {
   287            VCO_480          = 0xF1000000,  /*! VCO is 480 MHz */
   288            VCO_320          = 0xF0000000   /*! VCO is 320 MHz */
   289        }
   290    
   291        /*! Asserted in Boot_sysCtlClockSet */
   292        config Assert.Id A_mustUseEnhancedClockMode = {
   293            msg: "A_mustUseEnhancedClockMode: This device requires the Enhanced Clock Mode."
   294        };
   295    
   296        /*! Asserted in Boot_sysCtlClockFreqSet */
   297        config Assert.Id A_mustNotUseEnhancedClockMode = {
   298            msg: "A_mustNotUseEnhancedClockMode: This device does not support the Enhanced Clock Mode."
   299        };
   300    
   301    
   302        /*!
   303         *  Clock configuration flag, default is false.
   304         *
   305         *  Set to true to automatically configure the Clock.
   306         */
   307        metaonly config Bool configureClock = false;
   308    
   309        /*! SYS Clock Divisor */
   310        metaonly config SysDiv sysClockDiv = SYSDIV_1;
   311    
   312        /*! PWM Clock Divisor */
   313        metaonly config PwmDiv pwmClockDiv = PWMDIV_1;
   314    
   315        /*! Crystal Value */
   316        metaonly config XtalFreq xtal = XTAL_1MHZ;
   317    
   318        /*! Oscillator Source */
   319        metaonly config OscSrc oscSrc = OSCSRC_MAIN;
   320    
   321        /*! VCO frequency */
   322        metaonly config VcoFreq vcoFreq = VCO_320;
   323    
   324        /*! PLL Bypass flag */
   325        metaonly config Bool pllBypass = false;
   326    
   327        /*! PLL Output Enable flag */
   328        metaonly config Bool pllOutEnable = false;
   329    
   330        /*! Internal Oscillator Disable flag */
   331        metaonly config Bool ioscDisable = false;
   332    
   333        /*! Main Oscillator Disable flag */
   334        metaonly config Bool moscDisable = false;
   335    
   336        /*!
   337         *  @_nodoc
   338         *  LDO configuration flag, default is false.
   339         *
   340         *  Set to true to automatically configure the LDO.
   341         */
   342        metaonly config Bool configureLdo = false;
   343    
   344        /*!
   345         *  @_nodoc
   346         *  LDO VADJ setting, default is 2.5V
   347         */
   348        metaonly config LdoOut ldoOut = LDOPCTL_2_50V;
   349    
   350        /*!
   351         *  Enahnced Clocking Mode.
   352         *
   353         *  Must be set to true for OneMCU devices that support this feature.
   354         */
   355        metaonly config Bool enhancedClockMode = false;
   356    
   357        /*!
   358         *  Desired CPU Clock Frequency in Hz.
   359         *
   360         *  Configurable only on devices with "Enhanced Clocking Mode" support.
   361         */
   362        metaonly config UInt cpuFrequency = 40000000;
   363    
   364        /*
   365         *  @_nodoc
   366         *  ======== sysCtlClockSet ========
   367         *  wrapper for Boot_sysCtlClockSetI()
   368         *  verifies that this function is correct for this devices.
   369         *  then calls Boot_sysCtlClockSetI()
   370         *
   371         *  param ulConfig is the required configuration of the device clocking.
   372         */
   373        @DirectCall
   374        Void sysCtlClockSet(ULong ulConfig);
   375    
   376        /*
   377         *  @_nodoc
   378         *  ======== sysCtlClockFreqSet ========
   379         *  Configures the system clock.
   380         *
   381         *  wrapper for Boot_sysCtlClockFreqSetI()
   382         *  verifies that this function is correct for this devices.
   383         *  then calls Boot_sysCtlClockFreqSetI()
   384         *
   385         *  @param ulConfig is the required configuration of the device clocking.
   386         *  @param ulSysClock is the requested processor frequency.
   387         *
   388         *  @return The actual configured system clock frequency in Hz or zero if the
   389         *  value could not be changed due to a parameter error or PLL lock failure.
   390         */
   391        @DirectCall
   392        ULong sysCtlClockFreqSet(ULong ulConfig, ULong ulSysClock);
   393    
   394        /*!
   395         *  @_nodoc
   396         *  ======== registerFreqListener ========
   397         *  Register a module to be notified whenever the frequency changes.
   398         *
   399         *  The registered module must have a function named 'fireFrequencyUpdate'
   400         *  which takes the new frequency as an argument.
   401         */
   402        function registerFreqListener();
   403    
   404    internal:
   405    
   406        /*
   407         *  ======== sysCtlClockSetI ========
   408         *  Configures the system clock. (legacy function)
   409         *
   410         *  param ulConfig is the required configuration of the device clocking.
   411         */
   412        Void sysCtlClockSetI(ULong ulConfig);
   413    
   414        /*
   415         *  ======== sysCtlClockFreqSetI ========
   416         *  Configures the system clock.
   417         *
   418         *  @param ulConfig is the required configuration of the device clocking.
   419         *  @param ulSysClock is the requested processor frequency.
   420         *
   421         *  @return The actual configured system clock frequency in Hz or zero if the
   422         *  value could not be changed due to a parameter error or PLL lock failure.
   423         */
   424        ULong sysCtlClockFreqSetI(ULong ulConfig, ULong ulSysClock);
   425    
   426        /*
   427         *  ======== sysCtlDelayI ========
   428         *  Provides a small delay.
   429         *
   430         *  @param ulCount is the number of delay loop iterations to perform.
   431         */
   432        Void sysCtlDelayI(ULong ulCount);
   433    
   434        /*
   435         *  ======== init ========
   436         *  Generated entry point into clock initialization function.
   437         *
   438         *  Installed as a Startup.firstFxn.
   439         *  Calls either Boot_sysCtlClockSet() or Boot_sysCtlClockFreqSet()
   440         *  depending on value of 'Boot.enhancedClockMode'.
   441         */
   442        Void init();
   443    
   444        /*!
   445         *  computed RCC value based on settings
   446         */
   447        metaonly config UInt ulConfig;
   448    
   449        /*!
   450         *  computed cpu frequency based on clock settings
   451         */
   452        metaonly config UInt computedCpuFrequency;
   453    
   454    };