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37
38 package ti.catalog.arm.cortexm3.concertoInit;
39
40 import xdc.rov.ViewInfo;
41
42 /*!
43 * ======== Boot ========
44 * Concerto M3 Boot Support.
45 *
46 * The Boot module supports boot initialization for the Concerto M3 core.
47 * A special boot init function is created based on the configuration
48 * settings for this module. This function is hooked into the
49 * xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
50 * to cinit processing).
51 *
52 * The code to support the boot module is placed in a separate section
53 * named `".text:.bootCodeSection"` to allow placement of this section in
54 * the linker .cmd file if necessary. This section is a subsection of the
55 * `".text"` section so this code will be placed into the .text section unless
56 * explicitly placed, either through
57 * `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
58 * command file.
59 */
60 @Template("./Boot.xdt")
61 @NoRuntime
62 module Boot
63 {
64 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
65 metaonly enum FractMult {
66 Fract_0 = 0x000, /*! Fractional multiplier is 0 */
67 Fract_25 = 0x100, /*! Fractional multiplier is 0.25 */
68 Fract_50 = 0x200, /*! Fractional multiplier is 0.5 */
69 Fract_75 = 0x300 /*! Fractional multiplier is 0.75 */
70 }
71
72 /*! System Clock Divider (SYSDIVSEL) value */
73 metaonly enum SysDiv {
74 Div_1 = 0x0, /*! Divide by 1 */
75 Div_2 = 0x1, /*! Divide by 2 */
76 Div_4 = 0x2, /*! Divide by 4 */
77 Div_8 = 0x3 /*! Divide by 8 */
78 };
79
80 /*! M3 Subsystem Clock Divider (M3SSDIVSEL) value */
81 metaonly enum M3Div {
82 M3Div_1 = 0x0, /*! Divide by 1 */
83 M3Div_2 = 0x1, /*! Divide by 2 */
84 M3Div_4 = 0x2 /*! Divide by 4 */
85 };
86
87 metaonly struct ModuleView {
88 Bool configureClocks;
89 UInt OSCCLK;
90 UInt SPLLIMULT;
91 String SPLLFMULT;
92 String SYSDIVSEL;
93 String M3SSDIVSEL;
94 Bool bootC28;
95 }
96
97 @Facet
98 metaonly config ViewInfo.Instance rovViewInfo =
99 ViewInfo.create({
100 viewMap: [
101 [
102 'Module',
103 {
104 type: ViewInfo.MODULE,
105 viewInitFxn: 'viewInitModule',
106 structName: 'ModuleView'
107 }
108 ],
109 ]
110 });
111
112 /*!
113 * Flash controller configuration flag, default is true.
114 *
115 * Set to true to enable the configuration of the Flash controller
116 * wait states, program and data cache.
117 */
118 metaonly config Bool configureFlashController = true;
119
120 /*!
121 * Clock configuration flag, default is false.
122 *
123 * Set to true to configure the PLL and system and M3 subsystem clock
124 * dividers.
125 */
126 config Bool configureClocks = false;
127
128 /*!
129 * ======== sharedMemoryEnable ========
130 * Shared RAM memory enable mask.
131 *
132 * This parameter is used for writing the MEMCNF register.
133 * By default, all shared RAM segments will be enabled at runtime.
134 * To disable a shared RAM segment, set the corresponding bit to 0.
135 * If any data is loaded to a shared RAM segment, the segment must
136 * be enabled prior to loading the program through other means.
137 */
138 config Bits32 sharedMemoryEnable = 0xffffffff;
139
140 /*!
141 * ======== sharedMemoryOwnerMask ========
142 * Shared RAM owner select mask.
143 *
144 * This parameter is used for writing the MSxMSEL register.
145 * By default, each value of each shared RAM select bit is '0'.
146 * This means the M3 is the owner and has write access based upon
147 * the sharedMemoryAccess bits. Setting a '1' in any bit position
148 * makes the C28 the owner of that shared RAM segment.
149 */
150 config Bits32 sharedMemoryOwnerMask = 0;
151
152 /*!
153 * ======== sharedMemoryAccess ========
154 * Shared RAM M3 write access.
155 *
156 * This parameter is used for writing the MSxSRCR registers.
157 * It determines the M3 write access for each shared RAM segment only
158 * when the M3 is the owner of the shared RAM segment.
159 * By default, the M3 is allowed to CPU fetch, DMA write, and CPU write.
160 *
161 * Bit 0 is for CPU fetch. 0 - fetch allowed, 1 - fetch not allowed
162 * Bit 1 is for DMA write. 0 - write allowed, 1 - write not allowed
163 * Bit 2 is for CPU write. 0 - write allowed, 1 - write not allowed
164 */
165 config Bits32 sharedMemoryAccess[8];
166
167 /*!
168 * OSCCLK input frequency to PLL, in MHz. Default is 20 MHz.
169 *
170 * This is the frequency of the oscillator clock (OSCCLK) input to the
171 * PLL.
172 */
173 metaonly config UInt OSCCLK = 20;
174
175 /*! System PLL Integer Multiplier (SPLLIMULT) value */
176 metaonly config UInt SPLLIMULT = 1;
177
178 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
179 metaonly config FractMult SPLLFMULT = Fract_0;
180
181 /*! System Clock Divider (SYSDIVSEL) value */
182 metaonly config SysDiv SYSDIVSEL = Div_8;
183
184 /*! M3 Subsystem Clock Divider (M3SSDIVSEL) value */
185 metaonly config M3Div M3SSDIVSEL = M3Div_4;
186
187 /*!
188 * Flash controller wait states configuration flag, default is true.
189 *
190 * Set to true to configure the Flash controller wait states. The number
191 * of wait states is computed based upon the CPU frequency.
192 */
193 metaonly config Bool configureFlashWaitStates = true;
194
195 /*!
196 * Flash controller program cache enable flag, default is true.
197 *
198 * Set to true to enable the Flash controller's program cache.
199 */
200 metaonly config Bool enableFlashProgramCache = true;
201
202 /*!
203 * Flash controller data cache enable flag, default is true.
204 *
205 * Set to true to enable the Flash controller's data cache.
206 */
207 metaonly config Bool enableFlashDataCache = true;
208
209 /*!
210 * Function to be called when Limp mode is detected.
211 *
212 * This function is called when the Boot module is about to configure
213 * the PLL, but finds the device operating in Limp mode (i.e., the mode
214 * when a missing OSCCLK input has been detected).
215 *
216 * If this function is not specified by the application, a default
217 * function will be used, which spins in an infinite loop.
218 */
219 metaonly config Fxn limpAbortFunction;
220
221 /*!
222 * Boot from Flash flag. Default is true.
223 *
224 * Set to true to enable booting the M3 from Flash.
225 */
226 metaonly config Bool bootFromFlash = true;
227
228 /*!
229 * Initiate booting of the C28 processor. Default is false.
230 *
231 * Set to true to enable the M3 to initiate boot of the C28.
232 *
233 * If enabled, this will occur after the optional clock configuration
234 * step, enabled by `{@link #configureClocks}`.
235 */
236 metaonly config Bool bootC28 = false;
237
238 /*!
239 * Initialize C28 RAM regions before booting the C28 processor.
240 * Default is true.
241 *
242 * Set to true to enable initialization of these C28 RAM regions: M1,
243 * CtoM, LO, L1, L2, and L3. RAM locations will be zeroed, and the ECC or
244 * parity bits will be initialized.
245 */
246 metaonly config Bool initC28RAMs = true;
247
248 /*!
249 * Configure Shared RAM regions before booting the C28 processor.
250 * Default is true.
251 *
252 * Set to true to enable Shared RAM regions S0-S7, to set the
253 * owner of each region and the write access permissions for the onwer.
254 */
255 metaonly config Bool configSharedRAMs = true;
256
257 /*!
258 * ======== loadSegment ========
259 * Specifies where to load the flash function
260 *
261 * If 'configureFlashWaitStates' is true, then this parameter
262 * determines where the ".ti_catalog_c2800_initF2837x_flashfuncs"
263 * section gets loaded.
264 */
265 metaonly config String loadSegment;
266
267 /*!
268 * ======== runSegment ========
269 * Specifies where to run the flash function
270 *
271 * If 'configureFlashWaitStates' is true then this parameter
272 * determines where the ".ti_catalog_c2800_initF2837x_flashfuncs"
273 * section gets executed at runtime.
274 */
275 metaonly config String runSegment;
276
277 /*!
278 * @_nodoc
279 * ======== getFrequency ========
280 * Gets the resulting M3 CPU frequency (in Hz) given the Clock
281 * configuration parameters.
282 *
283 */
284 UInt32 getFrequency();
285
286 /*!
287 * @_nodoc
288 * ======== registerFreqListener ========
289 * Register a module to be notified whenever the frequency changes.
290 *
291 * The registered module must have a function named 'fireFrequencyUpdate'
292 * which takes the new frequency as an argument.
293 */
294 function registerFreqListener();
295
296 internal:
297
298
299 metaonly config UInt timestampFreq;
300
301
302 metaonly config String displayFrequency;
303
304
305 metaonly config String displayFrequency28;
306
307
308 metaonly config UInt flashWaitStates = 3;
309
310
311 metaonly config Bits32 MSxSRCR[2];
312
313 };