Texas Instruments

Table of Contents

IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 7.50.1.22

BIOS Version: bios_6_46_02_46_eng

XDCTools Version: xdctools_3_32_01_22

Benchmark Cycles
Interrupt Latency 119
Hwi_restore() 7
Hwi_disable() 9
Hwi dispatcher prolog 94
Hwi dispatcher epilog 194
Hwi dispatcher 278
Hardware Interrupt to Blocked Task 460
Hardware Interrupt to Software Interrupt 310
Swi_enable() 46
Swi_disable() 11
Post Software Interrupt Again 20
Post Software Interrupt without Context Switch 81
Post Software Interrupt with Context Switch 165
Create a New Task without Context Switch 1441
Set a Task Priority without a Context Switch 138
Task_yield() 180
Post Semaphore No Waiting Task 44
Post Semaphore No Task Switch 169
Post Semaphore with Task Switch 225
Pend on Semaphore No Context Switch 60
Pend on Semaphore with Task Switch 250
Clock_getTicks() 9
POSIX Create a New Task without Context Switch 2750
POSIX Set a Task Priority without a Context Switch 159
POSIX Post Semaphore No Waiting Task 57
POSIX Post Semaphore No Task Switch 181
POSIX Post Semaphore with Task Switch 225
POSIX Pend on Semaphore No Context Switch 53
POSIX Pend on Semaphore with Task Switch 238

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.