Texas Instruments

Table of Contents

GCC Cortex-M3 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC1350:1

Tool Chain Version: 4.9.3

BIOS Version: bios_6_46_02_46_eng

XDCTools Version: xdctools_3_32_01_22

Benchmark Cycles
Interrupt Latency 190
Hwi_restore() 20
Hwi_disable() 20
Hwi dispatcher prolog 118
Hwi dispatcher epilog 204
Hwi dispatcher 313
Hardware Interrupt to Blocked Task 541
Hardware Interrupt to Software Interrupt 389
Swi_enable() 85
Swi_disable() 22
Post Software Interrupt Again 45
Post Software Interrupt without Context Switch 110
Post Software Interrupt with Context Switch 220
Create a New Task without Context Switch 4643
Set a Task Priority without a Context Switch 177
Task_yield() 217
Post Semaphore No Waiting Task 69
Post Semaphore No Task Switch 211
Post Semaphore with Task Switch 274
Pend on Semaphore No Context Switch 80
Pend on Semaphore with Task Switch 309
Clock_getTicks() 269
POSIX Create a New Task without Context Switch 7518
POSIX Set a Task Priority without a Context Switch 268
POSIX Post Semaphore No Waiting Task 79
POSIX Post Semaphore No Task Switch 220
POSIX Post Semaphore with Task Switch 284
POSIX Pend on Semaphore No Context Switch 90
POSIX Pend on Semaphore with Task Switch 320

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:

“-mcpu=cortex-m3 -mthumb -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__”.

The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.