Target Platform: ti.platforms.simplelink:CC3200:1
Tool Chain Version: 7.50.1.22
BIOS Version: bios_6_46_02_46_eng
XDCTools Version: xdctools_3_32_01_22
Benchmark | Cycles |
---|---|
Interrupt Latency | 146 |
Hwi_restore() | 14 |
Hwi_disable() | 16 |
Hwi dispatcher prolog | 120 |
Hwi dispatcher epilog | 243 |
Hwi dispatcher | 355 |
Hardware Interrupt to Blocked Task | 593 |
Hardware Interrupt to Software Interrupt | 408 |
Swi_enable() | 60 |
Swi_disable() | 16 |
Post Software Interrupt Again | 23 |
Post Software Interrupt without Context Switch | 102 |
Post Software Interrupt with Context Switch | 209 |
Create a New Task without Context Switch | 1947 |
Set a Task Priority without a Context Switch | 183 |
Task_yield() | 233 |
Post Semaphore No Waiting Task | 51 |
Post Semaphore No Task Switch | 218 |
Post Semaphore with Task Switch | 291 |
Pend on Semaphore No Context Switch | 76 |
Pend on Semaphore with Task Switch | 319 |
Clock_getTicks() | 14 |
POSIX Create a New Task without Context Switch | 3724 |
POSIX Set a Task Priority without a Context Switch | 209 |
POSIX Post Semaphore No Waiting Task | 73 |
POSIX Post Semaphore No Task Switch | 243 |
POSIX Post Semaphore with Task Switch | 298 |
POSIX Pend on Semaphore No Context Switch | 70 |
POSIX Pend on Semaphore with Task Switch | 304 |
The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.
See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.