Texas Instruments

Table of Contents

TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 15.12.2

BIOS Version: bios_6_46_00_22_eng

XDCTools Version: xdctools_3_32_01_11_eng

Benchmark Cycles
Interrupt Latency 102
Hwi_restore() 1
Hwi_disable() 4
Hwi dispatcher prolog 90
Hwi dispatcher epilog 188
Hwi dispatcher 268
Hardware Interrupt to Blocked Task 446
Hardware Interrupt to Software Interrupt 303
Swi_enable() 59
Swi_disable() 10
Post Software Interrupt Again 29
Post Software Interrupt without Context Switch 86
Post Software Interrupt with Context Switch 160
Create a New Task without Context Switch 1567
Set a Task Priority without a Context Switch 135
Task_yield() 173
Post Semaphore No Waiting Task 42
Post Semaphore No Task Switch 163
Post Semaphore with Task Switch 218
Pend on Semaphore No Context Switch 61
Pend on Semaphore with Task Switch 225
Clock_getTicks() 8
POSIX Create a New Task without Context Switch 3074
POSIX Set a Task Priority without a Context Switch 215
POSIX Post Semaphore No Waiting Task 52
POSIX Post Semaphore No Task Switch 172
POSIX Post Semaphore with Task Switch 227
POSIX Pend on Semaphore No Context Switch 74
POSIX Pend on Semaphore with Task Switch 235

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.