Texas Instruments

Table of Contents

TI Cortex-M3 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC2650:1

Tool Chain Version: 15.12.2

BIOS Version: bios_6_46_00_22_eng

XDCTools Version: xdctools_3_32_01_11_eng

Benchmark Cycles
Interrupt Latency 123
Hwi_restore() 1
Hwi_disable() 2
Hwi dispatcher prolog 112
Hwi dispatcher epilog 205
Hwi dispatcher 307
Hardware Interrupt to Blocked Task 532
Hardware Interrupt to Software Interrupt 380
Swi_enable() 74
Swi_disable() 18
Post Software Interrupt Again 38
Post Software Interrupt without Context Switch 108
Post Software Interrupt with Context Switch 212
Create a New Task without Context Switch 4641
Set a Task Priority without a Context Switch 155
Task_yield() 213
Post Semaphore No Waiting Task 61
Post Semaphore No Task Switch 203
Post Semaphore with Task Switch 266
Pend on Semaphore No Context Switch 71
Pend on Semaphore with Task Switch 301
Clock_getTicks() 377
POSIX Create a New Task without Context Switch 7343
POSIX Set a Task Priority without a Context Switch 255
POSIX Post Semaphore No Waiting Task 73
POSIX Post Semaphore No Task Switch 214
POSIX Post Semaphore with Task Switch 277
POSIX Pend on Semaphore No Context Switch 87
POSIX Pend on Semaphore with Task Switch 316

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M3 –abi=eabi -ms –opt_for_speed=2 –program_level_compile -o3”.

The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.