Texas Instruments

Table of Contents

TI Cortex-M3 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC1350:1

Tool Chain Version: 15.12.2

BIOS Version: bios_6_46_00_22_eng

XDCTools Version: xdctools_3_32_01_11_eng

Benchmark Cycles
Interrupt Latency 119
Hwi_restore() 1
Hwi_disable() 2
Hwi dispatcher prolog 103
Hwi dispatcher epilog 211
Hwi dispatcher 304
Hardware Interrupt to Blocked Task 507
Hardware Interrupt to Software Interrupt 342
Swi_enable() 67
Swi_disable() 12
Post Software Interrupt Again 31
Post Software Interrupt without Context Switch 95
Post Software Interrupt with Context Switch 178
Create a New Task without Context Switch 4325
Set a Task Priority without a Context Switch 151
Task_yield() 185
Post Semaphore No Waiting Task 48
Post Semaphore No Task Switch 182
Post Semaphore with Task Switch 240
Pend on Semaphore No Context Switch 68
Pend on Semaphore with Task Switch 249
Clock_getTicks() 10
POSIX Create a New Task without Context Switch 6079
POSIX Set a Task Priority without a Context Switch 239
POSIX Post Semaphore No Waiting Task 60
POSIX Post Semaphore No Task Switch 193
POSIX Post Semaphore with Task Switch 251
POSIX Pend on Semaphore No Context Switch 84
POSIX Pend on Semaphore with Task Switch 264

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M3 –abi=eabi -ms –opt_for_speed=2 –program_level_compile -o3”.

The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.