Texas Instruments

Table of Contents

IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 7.50.1.22

BIOS Version: bios_6_46_00_22_eng

XDCTools Version: xdctools_3_32_01_11_eng

Benchmark Cycles
Interrupt Latency 147
Hwi_restore() 2
Hwi_disable() 2
Hwi dispatcher prolog 120
Hwi dispatcher epilog 241
Hwi dispatcher 352
Hardware Interrupt to Blocked Task 588
Hardware Interrupt to Software Interrupt 404
Swi_enable() 59
Swi_disable() 17
Post Software Interrupt Again 24
Post Software Interrupt without Context Switch 104
Post Software Interrupt with Context Switch 211
Create a New Task without Context Switch 1912
Set a Task Priority without a Context Switch 186
Task_yield() 232
Post Semaphore No Waiting Task 50
Post Semaphore No Task Switch 216
Post Semaphore with Task Switch 289
Pend on Semaphore No Context Switch 79
Pend on Semaphore with Task Switch 324
Clock_getTicks() 14
POSIX Create a New Task without Context Switch 3662
POSIX Set a Task Priority without a Context Switch 256
POSIX Post Semaphore No Waiting Task 75
POSIX Post Semaphore No Task Switch 239
POSIX Post Semaphore with Task Switch 298
POSIX Pend on Semaphore No Context Switch 69
POSIX Pend on Semaphore with Task Switch 305

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.