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SYS/BIOS 6.45.00.20 is a GA of SYS/BIOS 6.45. CCS users must use CCSv6.0.0 or higher.
Please read the SYS/BIOS User’s Guide for help installing and setting up your environment to use SYS/BIOS 6.45.00.20.
The following documentation is provided with this release. These documents are also available via the CCS Eclipse help table of contents.
License and manifest.
Additional online sources of documentation.
Release notes from previous releases are also available in the release notes archive directory.
SYS/BIOS 6.45.00.20 GA Release (this release).
| Bug ID | Headline |
|---|---|
| SDOCM00120211 | F2837x boot module’s loadSegment incorrect for some devices |
| SDOCM00120197 | cc32xx TimestampProvider should read RTC registers directly instead of using Timer APIs |
| SDOCM00120093 | DDR size in evmAM3359 Platform is incorrect and needs to be corrected |
| SDOCM00120003 | initF2837x Boot module needs to support setting the clock source register (CLKSRCCTL1) |
| SDOCM00119977 | initF2837x Boot module does not show Boot.disableWatchdog in xgconf |
| SDOCM00119940 | HeapBuf_create should check to make sure the blocksize is not too small for two pointers |
| SDOCM00119782 | BIOS pthread_join() should return EDEADLK for thread attempting to join self. |
| SDOCM00119702 | BIOS clock_gettime(), clock_settime() should not ignore the clock_id parameter |
| SDOCM00119688 | IAR configuro generates wrong output directory when cfg path contains backslash |
| SDOCM00119664 | Update IAR ROV .dll to fix problem with callstacks (which have been disabled for IAR temporarily in 6.42.03) |
| SDOCM00119567 | BIOS POSIX needs sleep and usleep functions |
| SDOCM00119537 | Fix misra defects related to the use of time handling functions from |
| SDOCM00119451 | Port/Validate BIOS examples for F28004x devices |
| SDOCM00119415 | Misra checker is not happy with the ‘#if ti_sysbios_knl_Clock_stopCheckNext__D’ in Clock.c |
| SDOCM00119242 | Look for ways to significantly improve the ROM build time for CC13xx/26xx ROM-based apps |
| SDOCM00119160 | BIOS.xs should not force -heap=0 when MemAlloc.generateFunctions = false |
| SDOCM00119104 | Update GCC compiler versions for all GNU targets to GCC v4.8 (2014q3) in the avala tree (SYS/BIOS dev tree) |
| SDOCM00119004 | Move the Power driver from the kernel to the drivers tree |
| SDOCM00119041 | ARM A8 Cache_disable API should not re-enable caches unless previously enabled |
| SDOCM00118933 | Cache_disable API for ARM Cortex A8 should disable interrupts |
| SDOCM00118896 | Updated TI linker .cmd files to have ‘.TI.ramfunc’ section to support the associated gcc __attribute__ |
| SDOCM00118694 | Update IPU/Benelli assembly files to support gcc for Cortex-M4 |
| SDOCM00118660 | Revisit ROV support for constructed objects |
| SDOCM00118659 | Remove TI A8F target support |
| SDOCM00118658 | Remove various old/stale packages from SYS/BIOS development tree (avala) |
| SDOCM00118657 | Remove MSP430 small model support |
| SDOCM00118656 | Remove Stellaris LM3xx/LM4xx support |
| SDOCM00118655 | Remove C64x+ (C64P) and Tesla (C64T) target support |
| SDOCM00118654 | Remove “whole program” release and debug profiles from all targets |
| SDOCM00118653 | Remove ti.sysbios.smp.Load module (ti.sysbios.utils.Load has SMP support and should be used instead) |
| SDOCM00118651 | update the MSP430 compiler to 4.4.x |
| SDOCM00118650 | Remove BIOS 5 legacy support package (i.e. ti.bios package) |
| SDOCM00118641 | Improve description of Hwi.MaskingOption, clarify MaskingOption_SELF for M3 |
| SDOCM00118640 | dual-core Cortex-M3/M4 SMP Core1 boot: Ensure ordering of writes of instruction and stack pointer |
| SDOCM00118639 | Tweaks to wording in GIO module description in User Guide |
| SDOCM00118617 | Add validation check to ensure Clock is not enabled when m3.Hwi.dispatcherSwiSupport is set false |
| SDOCM00118548 | Cache.setMarMeta needs better documentation |
| SDOCM00118417 | TI targets should use the compiler shell instead of invoking the linker directly |
| SDOCM00118415 | Add mfence trace workaround to instrumented builds of ti.sysbios.family.c66.Cache |
| SDOCM00118414 | Revisit CC3200 resetVector table (writing to a .const table) |
| SDOCM00118135 | Updates needed to SYS/BIOS UG and online benchmark documentation |
| SDOCM00117527 | Add a “packets” instance param to GIO module to allow application to pass a pointer to a buffer for packet block |
| SDOCM00117522 | Cache_startup() should be called as a reset function on AM44x/Cortex-A9 to setup L2 as SRAM early |
| SDOCM00117494 | ROM build flow creates extra/bogus Debug/src/sysbios directory in CCS project environment |
| SDOCM00117445 | Add support for Cortex-A15s on K2E, K2L and K2K devices (Keystone 2 family devices) |
| SDOCM00116667 | DMTimer’s Timer_Tsicr structure needs to be extended to support the new READ_MODE field |
| SDOCM00116538 | Make heap size easier to change for HeapMem (w/o requiring reconfig) |
| SDOCM00116098 | MSP430FR5969’s Boot module doesn’t show in XGCONF |
| SDOCM00116081 | Add a Memory Protection (MPU) module for Cortex-M devices |
| SDOCM00116009 | After refactoring a RTSC project or simply changing XDCTools version, the RTSC Target field gets changed. |
| SDOCM00115965 | Merge N-core and Dual-core Task Scheduling algorithm (SMP mode) |
| SDOCM00115666 | Hwi.xs should check if Hwi stack size (Program.stack) is aligned and align it if required |
| SDOCM00114997 | CC3200: Investigate option of Clock using SYSTICK together with sleep modes |
| SDOCM00114850 | Add Seconds module for MSP432 |
| SDOCM00114268 | SYS/BIOS User Guide should discuss FIFO vs Priority Semaphores |
| SDOCM00112605 | SYS/BIOS Task/Hwi checkStacks() should support stack overflow check when Task/Hwi initStackFlag is set to false |
| SDOCM00108096 | Task cdoc needs to explain Task hook run time context |
| SDOCM00104002 | move ti.sysbios.fatfs and fatfs.* packages to the TI-RTOS drivers tree and ship with TI-RTOS (not the kernel) |
| SDOCM00100978 | Add a BIOS_version macro for determining the SYS/BIOS version number |
Supported Operating Systems:
Minimum Required Software Versions:
Required Hardware
Click here for the list of supported devices.
Click here for the list of compilers used to build and validate this release (scroll down to Supported Targets section).
The following issues are known to affect this release:
For a full description of Benchmarks please see the appendices in the SYS/BIOS 6 User’s Guide.
All releases have 4 digits (M.mm.pp.bb). This includes GA and pre-releases (engineering, alpha/EA, beta, etc.). Pre-releases are denoted with a suffix (e.g. 6.30.00.00-eng or 6.30.00.10-beta).
This product’s version follows a version format, M.mm.pp.bb, where M is a single digit Major number, mm is 2 digit minor number, pp is a 2 digit patch number, and bb is an unrestricted set of digits used as an incrementing build counter.
To support multiple side-by-side installations of the product, the product version is encoded in the top level directory (e.g. bios_6_30_00_00).
Subsequent releases of patch upgrades will be identified by the patch number, ex. SYS/BIOS 6.30.01.15 with directory bios_6_30_01_15. Typically, these patches only include critical bug fixes.
Please note that version numbers and compatibility keys are NOT the same. For an explanation of compatibility keys, please refer to the Upgrade and Compatibility Information section.
Last updated: December 14, 2015 Build Ver: 6.45.00.20