GCC Cortex-M3 Timing Benchmarks

ti.platforms.tiva:TM4C123GH6PM:1 (compiler version: 4.7.3)

Benchmark Cycles (1)
Interrupt Latency 93 (2)
Hwi_restore() 3
Hwi_disable() 4
Hwi dispatcher prolog 117
Hwi dispatcher epilog 214
Hwi dispatcher 320
Hardware Interrupt to Blocked Task 628
Hardware Interrupt to Software Interrupt 368
Swi_enable() 64
Swi_disable() 11
Post Software Interrupt Again 30
Post Software Interrupt without Context Switch 84
Post Software Interrupt with Context Switch 180
Create a New Task without Context Switch 2165
Set a Task Priority without a Context Switch 157
Task_yield() 259
Post Semaphore, No Waiting Task 48
Post Semaphore No Task Switch 245
Post Semaphore with Task Switch 355
Pend on Semaphore, No Context Switch 50
Pend on Semaphore with Task Switch 365
Clock_getTicks() 9

(1) The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:

"-mcpu=cortex-m3 -mthumb -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__".

Timings were obtained using the Tiva Launchpad TM4C123GH6PM board running at 40MHz.

(2) The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.