1 /*
2 * Copyright (c) 2014, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /*
33 * ======== Cache.xdc ========
34 */
35
36 package ti.sysbios.family.arm.a15;
37
38 import xdc.rov.ViewInfo;
39
40 import xdc.runtime.Assert;
41
42 /*!
43 * ======== Cache ========
44 * ARM Cache Module
45 *
46 * This module manages the data and instruction caches on Cortex A15
47 * processors.
48 * It provides a list of functions that perform cache operations. The
49 * functions operate on a per cache line except for the 'All' functions
50 * which operate on the entire cache specified. Any Address that is not
51 * aligned to a cache line gets rounded down to the address of
52 * the nearest cache line.
53 *
54 * The L1 data and program caches as well as the L2 cache are enabled
55 * by default early during the startup sequence (prior to any
56 * Module_startup()s).
57 * Data caching requires the MMU to be enabled and the cacheable
58 * attribute of the section/page descriptor for a corresponding
59 * memory region to be enabled.
60 * Program caching does not require the MMU to be enabled and therefore
61 * occurs when the L1 program cache is enabled.
62 *
63 * (See the {@link ti.sysbios.family.arm.a15.Mmu} module for information
64 * about the MMU.)
65 *
66 * Note: The invalidate instruction is treated by A15 as a clean/invalidate
67 * instruction. Therefore, calls to Cache_inv()/Cache_invAll() will behave
68 * like Cache_wbInv()/Cache_wbInvAll() on A15.
69 *
70 * Unconstrained Functions
71 * All functions
72 *
73 * @p(html) 74 * <h3> Calling Context </h3>
75 * <table border="1" cellpadding="3">
76 * <colgroup span="1"></colgroup> <colgroup span="5" align="center">
77 * </colgroup>
78 *
79 * <tr><th> Function </th><th> Hwi </th><th> Swi </th>
80 * <th> Task </th><th> Main </th><th> Startup </th></tr>
81 * <!-- -->
82 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td>
83 * <td> Y </td><td> Y </td><td> Y </td></tr>
84 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td>
85 * <td> Y </td><td> Y </td><td> Y </td></tr>
86 * <tr><td> {@link #inv} </td><td> Y </td><td> Y </td>
87 * <td> Y </td><td> Y </td><td> Y </td></tr>
88 * <tr><td> {@link #invL1dAll} </td><td> Y </td><td> Y </td>
89 * <td> Y </td><td> Y </td><td> Y </td></tr>
90 * <tr><td> {@link #invL1pAll} </td><td> Y </td><td> Y </td>
91 * <td> Y </td><td> Y </td><td> Y </td></tr>
92 * <tr><td> {@link #wait} </td><td> Y </td><td> Y </td>
93 * <td> Y </td><td> Y </td><td> Y </td></tr>
94 * <tr><td> {@link #wb} </td><td> Y </td><td> Y </td>
95 * <td> Y </td><td> Y </td><td> Y </td></tr>
96 * <tr><td> {@link #wbInv} </td><td> Y </td><td> Y </td>
97 * <td> Y </td><td> Y </td><td> Y </td></tr>
98 * <tr><td> {@link #wbInvL1dAll} </td><td> Y </td><td> Y </td>
99 * <td> Y </td><td> Y </td><td> Y </td></tr>
100 * <tr><td> {@link #wbL1dAll} </td><td> Y </td><td> Y </td>
101 * <td> Y </td><td> Y </td><td> Y </td></tr>
102 * <tr><td> {@link #load} </td><td> Y </td><td> Y </td>
103 * <td> Y </td><td> Y </td><td> Y </td></tr>
104 * <tr><td colspan="6"> Definitions: <br />
105 * <ul>
106 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
107 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
108 * <li> <b>Task</b>: API is callable from a Task thread. </li>
109 * <li> <b>Main</b>: API is callable during any of these phases: </li>
110 * <ul>
111 * <li> In your module startup after this module is started
112 * (e.g. Cache_Module_startupDone() returns TRUE). </li>
113 * <li> During xdc.runtime.Startup.lastFxns. </li>
114 * <li> During main().</li>
115 * <li> During BIOS.startupFxns.</li>
116 * </ul>
117 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
118 * <ul>
119 * <li> During xdc.runtime.Startup.firstFxns.</li>
120 * <li> In your module startup before this module is started
121 * (e.g. Cache_Module_startupDone() returns FALSE).</li>
122 * </ul>
123 * </ul>
124 * </td></tr>
125 *
126 * </table>
127 * @p 128 */
129
130 module Cache inherits ti.sysbios.interfaces.ICache
131 {
132 /*!
133 * Size of L1 data cache Line in bytes
134 */
135 const UInt sizeL1dCacheLine = 64;
136
137 /*!
138 * Size of L1 program cache Line in bytes
139 */
140 const UInt sizeL1pCacheLine = 64;
141
142 /*!
143 * Size of L2 cache Line in bytes
144 */
145 const UInt sizeL2CacheLine = 64;
146
147 /*!
148 * ======== ModView ========
149 * @_nodoc 150 */
151 metaonlystruct CacheInfoView {
152 String cache;
153 SizeT cacheSize;
154 SizeT lineSize;
155 UInt ways;
156 SizeT waySize;
157 };
158
159 /*!
160 * ======== rovViewInfo ========
161 * @_nodoc 162 */
163 @Facet
164 metaonlyconfig ViewInfo.Instance rovViewInfo =
165 ViewInfo.create({
166 viewMap: [
167 ['Cache Info', { type: ViewInfo.MODULE_DATA,
168 viewInitFxn: 'viewInitCacheInfo',
169 structName: 'CacheInfoView'}]
170 ]
171 });
172
173 /*! Asserted in Cache_lock */
174 config Assert.Id A_badBlockLength = {
175 msg: "A_badBlockLength: Block length too large. Must be <= L2 way size."
176 };
177
178 /*! Asserted in Cache_lock */
179 config Assert.Id A_blockCrossesPage = {
180 msg: "A_blockCrossesPage: Memory block crosses L2 way page boundary."
181 };
182
183 /*!
184 * Enable L1 and L2 data and program caches.
185 *
186 * To enable a subset of the caches, set this parameter
187 * to 'false' and call Cache_enable() within main, passing it only
188 * the {@link Cache#Type Cache_Type(s)} to be enabled.
189 *
190 * Data caching requires the MMU and the memory section/page
191 * descriptor cacheable attribute to be enabled.
192 */
193 config Bool enableCache = true;
194
195 /*!
196 * Enable Branch Prediction at startup, default is true.
197 *
198 * This flag controls whether Branch Prediction should be automatically
199 * enabled or disabled during system startup.
200 *
201 * @a(NOTE) 202 * Upon reset, the A15's Program Flow Prediction (Branch Prediction)
203 * feature is disabled.
204 */
205 config Bool branchPredictionEnabled = true;
206
207 /*! @_nodoc 208 * ======== getEnabled ========
209 * Get the 'type' bitmask of cache(s) enabled.
210 */
211 Bits16 getEnabled();
212
213 /*!
214 * ======== invL1dAll ========
215 * Invalidate all of L1 data cache.
216 *
217 * This function should be used with caution. In general, the
218 * L1 data cache may contain some stack variable or valid data
219 * that should not be invalidated. This function should be used
220 * only when all contents of L1 data cache is unwanted.
221 */
222 Void invL1dAll();
223
224 /*!
225 * ======== invL1pAll ========
226 * Invalidate all of L1 program cache.
227 */
228 Void invL1pAll();
229
230 /*!
231 * ======== preLoad ========
232 * Loads a memory block into the L2 cache.
233 *
234 * A block of memory is loaded into the L2 cache.
235 *
236 * The memory block is loaded into cache one L2 cache line at time.
237 *
238 * The byteCnt argument must be less than or equal to an L2 cache
239 * size. An assert is generated if this rule is violated.
240 *
241 * Except for the normal L1 instruction cache behavior
242 * during code execution, the L1 instruction cache is
243 * unaffected by this API.
244 * The L1 data cache will be temporarily polluted by the contents
245 * of the referenced memory block.
246 *
247 * @a(NOTE) 248 * Interrupts are disabled for the entire time the memory block
249 * is being loaded into cache. For this reason, use of this API
250 * is probably best at system intialization time
251 * (ie: within 'main()').
252 *
253 * @param(blockPtr) start address of range to be loaded
254 * @param(byteCnt) number of bytes to be loaded
255 */
256 Void preLoad(Ptr blockPtr, SizeT byteCnt);
257
258 /*!
259 * ======== enableBP ========
260 * Enable Branch Prediction
261 *
262 * Calling this API will enable branch prediction.
263 *
264 * @a(NOTE) 265 * Upon reset, the A15's Program Flow Prediction (Branch Prediction)
266 * feature is disabled.
267 */
268 Void enableBP();
269
270 /*!
271 * ======== disableBP ========
272 * Disable Branch Prediction
273 *
274 * Calling this API will disable branch prediction.
275 *
276 * @a(NOTE) 277 * Upon reset, the A15's Program Flow Prediction (Branch Prediction)
278 * feature is disabled.
279 */
280 Void disableBP();
281
282 /*!
283 * @_nodoc 284 * ======== wbAllLoUIS ========
285 * Write back all caches to PoU for an Inner Shareable domain
286 *
287 * This function writes back the data cache. There is no effect
288 * on program cache. All data cache lines are left valid.
289 *
290 * On Cortex-A15, this function will write back the local CPU's
291 * L1 data cache. This API should be called with Hwis and/or Tasking
292 * disabled to guarantee the write back operation is complete.
293 */
294 Void wbAllLoUIS();
295
296 /*!
297 * @_nodoc 298 * ======== wbInvAllLoUIS ========
299 * Write back invalidate all caches to PoU for an Inner Shareable domain
300 *
301 * On Cortex-A15, this function will write back and invalidate the local
302 * CPU's L1 data cache. This API should be called with Hwis and/or Tasking
303 * disabled to guarantee the write back invalidate operation is complete.
304 */
305 Void wbInvAllLoUIS();
306
307 /*!
308 * ======== invBPAll ========
309 * Invalidate all branch predictors
310 *
311 * Invalidates all branch predictors on this core. If running in SMP mode,
312 * this operation is broadcast to all other cores.
313 */
314 Void invBPAll();
315
316 internal:
317
318 /*
319 * ======== initModuleState ========
320 * Initializes the module state.
321 *
322 * This function initializes module state fields like
323 * L1/L2 cache size and number of cache lines/sets. It
324 * is registered as a first function.
325 */
326 Void initModuleState();
327
328 /*
329 * ======== startup ========
330 * startup function to enable cache early during climb-up
331 */
332 Void startup();
333
334 /*
335 * ======== disableL1D ========
336 * Disable data cache
337 *
338 * This function disables the L1 data cache before performing
339 * a "write back invalidate all" of data and instruction caches.
340 *
341 * The L2 unified cache cannot be disabled on Cortex-A15.
342 * Disabling the L1 data cache effectively disables the L2 unified
343 * cache for all data caching purposes (on the current core in a
344 * Cortex-A15 multi-core system).
345 */
346 Void disableL1D();
347
348 /*
349 * ======== disableL1P ========
350 * Disable instruction cache
351 *
352 * This function disables the L1 instruction cache before
353 * performing a "invalidate all" of the whole instruction
354 * cache.
355 *
356 * The L2 unified cache cannot be disabled on Cortex-A15.
357 * Disabling the L1 instruction cache effectively disables the
358 * L2 unified cache for all instruction caching purposes (on
359 * the current core in a Cortex-A15 multi-core system).
360 */
361 Void disableL1P();
362
363 /*
364 * ======== enableL1D ========
365 * Enable data cache.
366 *
367 * This function enables the L1 data cache.
368 *
369 * Enabling the L1 data cache effectively enables the L2 unified
370 * cache for all data caching purposes (on the current core in a
371 * Cortex-A15 multi-core system).
372 */
373 Void enableL1D();
374
375 /*
376 * ======== enableL1P ========
377 * Enable instruction cache.
378 *
379 * This function enables the L1 instruction cache.
380 *
381 * Enabling the L1 instruction cache effectively enables the
382 * L2 unified cache for all instruction caching purposes (on
383 * the current core in a Cortex-A15 multi-core system).
384 *
385 * If the MMU is disabled and the L1 instruction cache is enabled,
386 * no new instructions will be cached in the L2 unified cache.
387 * However, code already cached in the L2 cache will be fetched.
388 */
389 Void enableL1P();
390
391 /*
392 * ======== invL1d ========
393 * Invalidates range in L1 data cache.
394 */
395 Void invL1d(Ptr blockPtr, SizeT byteCnt, Bool wait);
396
397 /*
398 * ======== invL1p ========
399 * Invalidates range in L1 program cache.
400 */
401 Void invL1p(Ptr blockPtr, SizeT byteCnt, Bool wait);
402
403 /*
404 * ======== preFetch ========
405 * load a block of memory into the L2 cache.
406 */
407 Void preFetch(Ptr blockPtr, SizeT byteCnt);
408
409 /*
410 * ======== getCacheLevelInfo ========
411 * returns Cache Size Id Register of corresponding Cache level
412 *
413 * level values
414 * 0 = L1D
415 * 1 = L1P
416 * 2 = L2
417 */
418 Bits32 getCacheLevelInfo(UInt level);
419
420 struct Module_State {
421 Bits32 l1dInfo;
422 Bits32 l1pInfo;
423 Bits32 l2Info;
424 SizeT l2WaySize;
425 }
426 }