1    /*
     2     * Copyright (c) 2013, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    /*
    33     *  ======== AMMU.xdc ========
    34     *
    35     */
    36    
    37    package ti.sysbios.hal.ammu;
    38    
    39    import xdc.rov.ViewInfo;
    40    
    41    /*! 
    42     *  ======== AMMU ========
    43     *  Attribute MMU configuration module
    44     *
    45     *  Responsible for initializing the Attribute MMU
    46     *
    47     *  @a(Restrictions)
    48     *  When used within a dual M3 core (Ducati) arrangement, care must be
    49     *  taken when initializing this shared resource. 
    50     *  The "Shared Resources" note provided
    51     *  in the {@link ti.sysbios.family.arm.ducati ducati} package discusses
    52     *  the management of the various hardware and software resources
    53     *  shared by the two M3 cores.
    54     *
    55     *  As the AMMU is shared between the two M3 cores, it should only
    56     *  be initialized and enabled once.
    57     *  It is intended that Core 0 will {@link #configureAmmu configure} 
    58     *  the AMMU at startup.
    59     *  @a
    60     */
    61    
    62    @DirectCall
    63    module AMMU
    64    {
    65        // -------- xgconf config filters --------
    66    
    67        /*! @_nodoc */
    68        metaonly readonly config xdc.runtime.Types.ViewInfo filteredNameMap$[string] = [
    69            ["Filtered Variables", {viewType: "module", viewFxn: "pageSizeFilter",
    70            fields: [
    71                "largePages", "mediumPages", "smallPages"
    72            ]}],
    73        ];
    74    
    75        /*! @_nodoc */
    76        metaonly any pageSizeFilter(int op, string paramName, string value);
    77    
    78        // -------- ROV views --------
    79        
    80        /*! @_nodoc */
    81        metaonly struct PageView {
    82            String      Page;
    83            Ptr         AddrVirtual;
    84            String      AddrPhysical;
    85            Bool        Enabled;
    86            Bool        L1Cacheable;
    87            String      L1WrPolicy;
    88            String      L1AllocPolicy;
    89            Bool        L1Posted;
    90            Bool        L2Cacheable;
    91            String      L2WrPolicy;
    92            String      L2AllocPolicy;
    93            Bool        L2Posted;
    94            Bool        ReadOnly;
    95            Bool        ExecOnly;
    96        };
    97    
    98        /*! @_nodoc */
    99        @Facet
   100        metaonly config ViewInfo.Instance rovViewInfo = 
   101            ViewInfo.create({
   102                viewMap: [
   103                    ['PageView',  {type: ViewInfo.MODULE_DATA, 
   104                      viewInitFxn: 'viewPages',
   105                      structName: 'PageView'}]
   106               ]
   107           });
   108    
   109        /* 
   110         * Policy register field definitions
   111         */
   112    
   113        metaonly enum Small {
   114            Small_4K,
   115            Small_8K,
   116            Small_16K,
   117            Small_32K
   118        };
   119    
   120        metaonly enum Medium {
   121            Medium_128K,
   122            Medium_256K,
   123            Medium_512K,
   124            Medium_1M
   125        };
   126    
   127        metaonly enum Large {
   128            Large_2M,
   129            Large_4M,
   130            Large_8M,
   131            Large_16M,
   132            Large_32M,
   133            Large_64M,
   134            Large_128M,
   135            Large_256M,
   136            Large_512M
   137        };
   138    
   139        metaonly enum Volatile {
   140            Volatile_DO_NOT_FOLLOW,
   141            Volatile_FOLLOW
   142        };
   143    
   144        metaonly enum CachePolicy {
   145            CachePolicy_NON_CACHEABLE,
   146            CachePolicy_CACHEABLE
   147        };
   148    
   149        metaonly enum PostedPolicy {
   150            PostedPolicy_NON_POSTED,
   151            PostedPolicy_POSTED
   152        };
   153    
   154        metaonly enum AllocatePolicy {
   155            AllocatePolicy_NON_ALLOCATE,
   156            AllocatePolicy_ALLOCATE
   157        };
   158    
   159        metaonly enum WritePolicy {
   160            WritePolicy_WRITE_THROUGH,
   161            WritePolicy_WRITE_BACK
   162        };
   163    
   164        metaonly enum Enable {
   165            Enable_NO,
   166            Enable_YES
   167        };
   168    
   169        /* 
   170         * Page Descriptor Definitions
   171         */
   172    
   173        metaonly struct LargePage {
   174            Enable          pageEnabled;
   175            Ptr             logicalAddress;
   176    
   177            Enable          translationEnabled;
   178            Ptr             translatedAddress;
   179    
   180            Large           size;
   181            Volatile        volatileQualifier;
   182            Enable          executeOnly;
   183            Enable          readOnly;
   184            Enable          prefetch;
   185            Enable          exclusion;
   186            CachePolicy     L1_cacheable;
   187            PostedPolicy    L1_posted;
   188            AllocatePolicy  L1_allocate;
   189            WritePolicy     L1_writePolicy;
   190            CachePolicy     L2_cacheable;
   191            PostedPolicy    L2_posted;
   192            AllocatePolicy  L2_allocate;
   193            WritePolicy     L2_writePolicy;
   194        };
   195    
   196        metaonly struct MediumPage {
   197            Enable          pageEnabled;
   198            Ptr             logicalAddress;
   199    
   200            Enable          translationEnabled;
   201            Ptr             translatedAddress;
   202    
   203            Medium          size;
   204            Volatile        volatileQualifier;
   205            Enable          executeOnly;
   206            Enable          readOnly;
   207            Enable          prefetch;
   208            Enable          exclusion;
   209            CachePolicy     L1_cacheable;
   210            PostedPolicy    L1_posted;
   211            AllocatePolicy  L1_allocate;
   212            WritePolicy     L1_writePolicy;
   213            CachePolicy     L2_cacheable;
   214            PostedPolicy    L2_posted;
   215            AllocatePolicy  L2_allocate;
   216            WritePolicy     L2_writePolicy;
   217        };
   218    
   219        metaonly struct SmallPage {
   220            Enable          pageEnabled;
   221            Ptr             logicalAddress;
   222    
   223            Enable          translationEnabled;
   224            Ptr             translatedAddress;
   225    
   226            Small           size;
   227            Volatile        volatileQualifier;
   228            Enable          executeOnly;
   229            Enable          readOnly;
   230            Enable          prefetch;
   231            Enable          exclusion;
   232            CachePolicy     L1_cacheable;
   233            PostedPolicy    L1_posted;
   234            AllocatePolicy  L1_allocate;
   235            WritePolicy     L1_writePolicy;
   236            CachePolicy     L2_cacheable;
   237            PostedPolicy    L2_posted;
   238            AllocatePolicy  L2_allocate;
   239            WritePolicy     L2_writePolicy;
   240        }
   241    
   242        metaonly enum Maintenance {
   243            DO_NOT_PERFORM,
   244            PERFORM
   245        };
   246    
   247        metaonly enum Invalidate {
   248            DO_NOT_INVALIDATE,
   249            INVALIDATE
   250        };
   251    
   252        metaonly enum Unlock {
   253            DO_NOT_UNLOCK,
   254            UNLOCK
   255        };
   256    
   257        metaonly enum Lock {
   258            DO_NOT_LOCK,
   259            LOCK
   260        };
   261    
   262        metaonly enum Clean {
   263            DO_NOT_CLEAN,
   264            CLEAN
   265        };
   266    
   267        metaonly struct SmallPageMaintenance {
   268            Maintenance     maintL2Cache;
   269            Maintenance     maintL1Cache2;
   270            Maintenance     maintL1Cache1;
   271            Enable          cpuInterrupt;
   272            Enable          hostInterrupt;
   273            Invalidate      invalidate;
   274            Clean           clean;
   275            Unlock          unlock;
   276            Lock            lock;
   277            Enable          preload;
   278        };
   279    
   280        metaonly struct LinePage {
   281            Enable          pageEnabled;
   282            Ptr             logicalAddress;
   283    
   284            Enable          translationEnabled;
   285            Ptr             translatedAddress;
   286        };
   287    
   288        metaonly struct DebugPage {
   289            Enable          pageEnabled;
   290            Enable          translationEnabled;
   291            Ptr             translatedAddress;
   292        };
   293    
   294        /*! The number of Large Page Desciptors is target/device specific */
   295        metaonly config LargePage largePages[] = [];
   296    
   297        /*! The number of Medium Page Desciptors is target/device specific */
   298        metaonly config MediumPage mediumPages[] = [];
   299    
   300        /*! The number of Small Page Desciptors is target/device specific */
   301        metaonly config SmallPage smallPages[] = [];
   302    
   303        /*! The number of Line Page Desciptors is target/device specific */
   304        metaonly config LinePage linePages[] = [];
   305    
   306        metaonly config DebugPage debugPage;
   307    
   308        /*
   309         * Runtime representation of the MMU registers
   310         */
   311        struct MMU {
   312            Char *LARGE_ADDR[8];    /* 0800 - 001C */
   313            Char *LARGE_XLTE[8];    /* 0820 - 003C */
   314            UInt32 LARGE_POLICY[8]; /* 0840 - 005C */
   315    
   316            Char *MEDIUM_ADDR[16];  /* 0860 - 009C */
   317            Char *MEDIUM_XLTE[16];  /* 08A0 - 00DC */
   318            UInt32 MEDIUM_POLICY[16]; /* 08E0 - 011C */
   319    
   320            Char *SMALL_ADDR[32];   /* 0920 - 019C */
   321            Char *SMALL_XLTE[32];   /* 09A0 - 021C */
   322            UInt32 SMALL_POLICY[32];/* 0A20 - 029C */
   323            UInt32 SMALL_MAINT[32]; /* 0AA0 - 031c */
   324    
   325            Char *LINE_ADDR[32];    /* 0B20 - 0B9C */
   326            Char *LINE_XLTE[32];    /* 0BA0 - 041C */
   327            UInt32 LINE_POLICY[32]; /* 0C20 - 049C */
   328    
   329            Char *DEBUG_XLTE;               /* 0CA0 */
   330            UInt32 DEBUG_POLICY;    /* 0CA4 */
   331    
   332            UInt32 MAINT;           /* 0CA8 */
   333            Char *MSTART;           /* 0CAC */
   334            Char *MEND;             /* 0CB0 */
   335            UInt32 MSTAT;           /* 0CB4 */
   336        };
   337    
   338        /*! 
   339         *  This device's AMMU register set address.
   340         *  Initialized internally according to build target/device.
   341         */
   342        extern volatile MMU mmu;
   343    
   344        /*! 
   345         * By default the AMMU module will configure the AMMU at startup.
   346         *
   347         * By setting this flag to false (ie for Ducati core1), the AMMU
   348         * module APIs are available but the initialization step is suppressed.
   349         */
   350        config Bool configureAmmu = true;
   351    
   352        /*!
   353         *  ======== invAll ========
   354         *  Invalidate entire L1 and L2 caches
   355         *  Waits for completion.
   356         */
   357        Void invAll();
   358    
   359        /*!
   360         *  @_nodoc
   361         *  ======== dumpAmmu ========
   362         *  formatted dump of the contents of the AMMU registers
   363         */
   364        Void dumpAmmu();
   365    
   366    internal:
   367    
   368        config UInt numLargePages;
   369        config UInt numMediumPages;
   370        config UInt numSmallPages;
   371        config UInt numLinePages;
   372    
   373        /* base address of mmu registers */
   374        metaonly config Ptr baseAddr;
   375    
   376        /* const image of intial mmu register values */
   377        config MMU mmuInitConfig;
   378        
   379        /* String names of page sizes */
   380        metaonly config String largePageSizeStrings[];
   381        metaonly config String mediumPageSizeStrings[];
   382        metaonly config String smallPageSizeStrings[];
   383    
   384        /* MMU initialization function called at startup */
   385        Void init();
   386    }
   387