TI Cortex-M4 with hard FP Timing Benchmarks

ti.platforms.stellaris:LM4F120H5QR:1 (compiler version: 5.1.1)

Benchmark Cycles (1)
Interrupt Latency 115 (2)
Hwi_restore() 1
Hwi_disable() 4
Hwi dispatcher prolog 112
Hwi dispatcher epilog 211
Hwi dispatcher() 314
Hardware Interrupt to Blocked Task 486
Hardware Interrupt to Software Interrupt 321
Swi_enable() 60
Swi_disable() 12
Post Software Interrupt Again 28
Post Software Interrupt without Context Switch 86
Post Software Interrupt with Context Switch 170
Create a New Task without Context Switch 1617
Set a Task Priority without a Context Switch 134
Task_yield 193
Post Semaphore, No Waiting Task 43
Post Semaphore No Task Switch 152
Post Semaphore with Task Switch 233
Pend on Semaphore, No Context Switch 55
Pend on Semaphore with Task Switch 239
Clock_getTicks 8

(1) The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: "--endian=little -mv7M4 --abi=eabi --float_support=fpv4spd16 -ms --opt_for_speed=2 --program_level_compile -o3".

Timings were obtained using the Tiva Launchpad TM4C123GH6PM board running at 40MHz.

(2) The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.