| Benchmark | Cycles | (1) |
| Interrupt Latency | 93 | (2) |
| Hwi_restore() | 1 | |
| Hwi_disable() | 4 | |
| Hwi dispatcher prolog | 117 | |
| Hwi dispatcher epilog | 216 | |
| Hwi dispatcher() | 321 | |
| Hardware Interrupt to Blocked Task | 624 | |
| Hardware Interrupt to Software Interrupt | 367 | |
| Swi_enable() | 60 | |
| Swi_disable() | 11 | |
| Post Software Interrupt Again | 30 | |
| Post Software Interrupt without Context Switch | 116 | |
| Post Software Interrupt with Context Switch | 195 | |
| Create a New Task without Context Switch | 2181 | |
| Set a Task Priority without a Context Switch | 156 | |
| Task_yield | 254 | |
| Post Semaphore, No Waiting Task | 48 | |
| Post Semaphore No Task Switch | 245 | |
| Post Semaphore with Task Switch | 350 | |
| Pend on Semaphore, No Context Switch | 50 | |
| Pend on Semaphore with Task Switch | 360 | |
| Clock_getTicks | 9 |
(1) The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:
"-mcpu=cortex-m3 -mthumb -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__".
Timings were obtained using the Tiva Launchpad TM4C123GH6PM board running at 40MHz.
(2) The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.