| Benchmark | Cycles | (1) |
| Interrupt latency | 93 | (2) |
| Hwi_enable | 1 | |
| Hwi_disable | 3 | |
| Hwi dispatcher prolog | 118 | |
| Hwi dispatcher epilog | 211 | |
| Hwi dispatcher | 322 | |
| Hardware Interrupt to Blocked Task | 628 | |
| Hardware Interrupt to Software Interrupt | 362 | |
| Swi_enable | 60 | |
| Swi_disable | 11 | |
| Post Software Interrupt Again | 31 | |
| Post Software Interrupt without Context Switch | 114 | |
| Post Software Interrupt with Context Switch | 199 | |
| Create a New Task without Context Switch | 2106 | |
| Set a Task Priority without a Context Switch | 211 | |
| Task_yield | 240 | |
| Post Semaphore, No Waiting Task | 51 | |
| Post Semaphore No Task Switch | 248 | |
| Post Semaphore with Task Switch | 353 | |
| Pend on Semaphore, No Context Switchi | 52 | |
| Pend on Semaphore with Task Switch | 349 | |
| Clock_getTicks | 9 |
(1) The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:
"-mcpu=cortex-m3 -mthumb -mabi=aapcs -O3 -g -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__".
Timings were obtained using the Stellaris Launchpad LM4F120 board running at 40MHz.
(2) The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.