| Benchmark | Cycles | (1) |
| Interrupt latency | 496 | |
| Hwi_enable | 46 | |
| Hwi_disable | 65 | |
| Hwi dispatcher prolog | 715 | |
| Hwi dispatcher epilog | 360 | |
| Hwi dispatcher | 771 | |
| Hardware Interrupt to Blocked Task | 1192 | |
| Hardware Interrupt to Software Interrupt | 814 | |
| Swi_enable | 291 | |
| Swi_disable | 0 | |
| Post Software Interrupt Again | 140 | |
| Post Software Interrupt without Context Switch | 322 | |
| Post Software Interrupt with Context Switch | 374 | |
| Create a New Task without Context Switch | 2122 | |
| Set a Task Priority without a Context Switch | 366 | |
| Task_yield | 545 | |
| Post Semaphore, No Waiting Task | 136 | |
| Post Semaphore No Task Switch | 532 | |
| Post Semaphore with Task Switch | 687 | |
| Pend on Semaphore, No Context Switchi | 142 | |
| Pend on Semaphore with Task Switch | 589 | |
| Clock_getTicks | 0 |
(1) The benchmark application was built using BIOS.LibType_Custom with the following compiler options: "-mcpu=cortex-a15 -mfpu=neon -mfloat-abi=hard -mabi=aapcs -mapcs-frame -ffunction-sections -fdata-sections -O3".
Timings were obtained using the sdp5430 evaluation board.
The A15 core was running at 800MHz, with L1 & L2 caches enabled, and all code & data placed in External RAM starting at 0x80000000.
To maximize cache performance, all code and data are prefetched into the L2 cache prior to collecting the performance numbers.
Unlike other target benchmarks that are collected using flat memory simulators or hardware with zero wait-state memory and no cache, these A15F numbers are collected on a real board with cache enabled. These numbers are effected by varying amounts of cache filling depending on the dynamics of the cache and the previous function calls.