| Benchmark | Cycles | (1) |
| Interrupt latency | 85 | (2) |
| Hwi_enable | 1 | |
| Hwi_disable | 6 | |
| Hwi dispatcher prolog | 91 | |
| Hwi dispatcher epilog | 191 | |
| Hwi dispatcher | 275 | |
| Hardware Interrupt to Blocked Task | 443 | |
| Hardware Interrupt to Software Interrupt | 298 | |
| Swi_enable | 59 | |
| Swi_disable | 12 | |
| Post Software Interrupt Again | 30 | |
| Post Software Interrupt without Context Switch | 97 | |
| Post Software Interrupt with Context Switch | 157 | |
| Create a New Task without Context Switch | 1586 | |
| Set a Task Priority without a Context Switch | 168 | |
| Task_yield | 158 | |
| Post Semaphore, No Waiting Task | 46 | |
| Post Semaphore No Task Switch | 162 | |
| Post Semaphore with Task Switch | 212 | |
| Pend on Semaphore, No Context Switchi | 58 | |
| Pend on Semaphore with Task Switch | 201 | |
| Clock_getTicks | 8 |
(1) The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: "--endian=little -mv7M3 --abi=eabi -ms --opt_for_speed=2 --program_level_compile -o3".
Timings were obtained using the Stellaris Blizzard LM4FSXLH5BB board running at 40MHz.
(2) The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.