1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
32 33 34 35
36 package ti.sysbios.family.arm.a8.intcps;
37
38 import xdc.rov.ViewInfo;
39
40 import xdc.runtime.Diags;
41 import xdc.runtime.Log;
42 import xdc.runtime.Error;
43
44 import ti.sysbios.BIOS;
45 import ti.sysbios.interfaces.IHwi;
46
47 /*!
48 * ======== Hwi ========
49 * Hardware Interrupt Support Module.
50 *
51 * This Hwi module provides ARM family-specific implementations of the
52 * APIs defined in {@link ti.sysbios.interfaces.IHwi IHwi}.
53 *
54 * Additional ARM device-specific APIs are also provided.
55 *
56 * @a(NOTE)
57 * In this Hwi module implementation, the instance config parameter value
58 * {@link #MaskingOption_LOWER} is equivalent to {@link #MaskingOption_SELF}.
59 * Statically configuring a Hwi object's {@link #Params.maskSetting} to
60 * {@link #MaskingOption_LOWER} will result in the generation of a benign
61 * build warning. Dynamic usages of {@link #MaskingOption_LOWER} will be
62 * silently converted to {@link #MaskingOption_SELF}.
63 *
64 */
65
66 @Template("./Hwi.xdt")
67 @ModuleStartup
68
69 module Hwi inherits ti.sysbios.interfaces.IHwi
70 {
71
72
73
74 /*! intcps supports 128 interrupts. */
75 const Int NUM_INTERRUPTS = 128;
76
77 /*!
78 * The device-specific number of priorities supported.
79 *
80 * The actual number supported is device specific and provided by
81 * the catalog device specification.
82 */
83 config Int NUM_PRIORITIES;
84
85
86
87 /*! Hwi vector function type definition. */
88 typedef Void (*VectorFuncPtr)(void);
89
90 /*!
91 * ======== BasicView ========
92 * @_nodoc
93 */
94 metaonly struct BasicView {
95 Ptr halHwiHandle;
96 String label;
97 Int intNum;
98 UInt priority;
99 String fxn;
100 UArg arg;
101 };
102
103 /*!
104 * ======== DetailedView ========
105 * @_nodoc
106 */
107 metaonly struct DetailedView {
108 Ptr halHwiHandle;
109 String label;
110 Int intNum;
111 UInt priority;
112 String fxn;
113 UArg arg;
114 Ptr irp;
115 Bool enabled;
116 Bool pending;
117 };
118
119 /*!
120 * ======== ModuleView ========
121 * @_nodoc
122 */
123 metaonly struct ModuleView {
124 String options[4];
125 UInt spuriousInterrupts;
126 UInt lastSpuriousInterrupt;
127 SizeT hwiStackPeak;
128 SizeT hwiStackSize;
129 Ptr hwiStackBase;
130 };
131
132 /*!
133 * ======== rovViewInfo ========
134 * @_nodoc
135 */
136 @Facet
137 metaonly config ViewInfo.Instance rovViewInfo =
138 ViewInfo.create({
139 viewMap: [
140 ['Basic', {type: ViewInfo.INSTANCE, viewInitFxn: 'viewInitBasic', structName: 'BasicView'}],
141 ['Detailed', {type: ViewInfo.INSTANCE, viewInitFxn: 'viewInitDetailed', structName: 'DetailedView'}],
142 ['Module', {type: ViewInfo.MODULE, viewInitFxn: 'viewInitModule', structName: 'ModuleView'}]
143 ]
144 });
145
146 /*! Interrupt type. IRQ or FIQ */
147 enum Type {
148 Type_IRQ, /*! IRQ interrupt. */
149 Type_FIQ /*! FIQ interrupt. */
150 };
151
152 /*! Interrupt Controller. Symbol "Hwi_intc" is physical device */
153 struct Intc {
154 UInt32 REVISION; /*! 0x00 Config Register */
155
156 UInt32 hole0[3]; /*! 0x04-0x0C */
157
158 UInt32 SYSCONFIG; /*! 0x10 Config Register */
159 UInt32 SYSSTATUS; /*! 0x14 Status Register */
160
161 UInt32 hole1[10]; /*! 0x18-0x3c */
162
163 UInt32 SIR_IRQ; /*! 0x40 Source IRQ Register */
164 UInt32 SIR_FIQ; /*! 0x44 Source FIQ Register */
165 UInt32 CONTROL; /*! 0x48 Control Register */
166 UInt32 PROTECTION; /*! 0x4C Protection Register */
167 UInt32 IDLE; /*! 0x50 Idle Register */
168
169 UInt32 hole2[3]; /*! 0x54-0x5C */
170
171 UInt32 IRQ_PRIORITY; /*! 0x60 IRQ Priority Register */
172 UInt32 FIQ_PRIORITY; /*! 0x64 IRQ Priority Register */
173 UInt32 THRESHOLD; /*! 0x68 Threshold Register */
174
175 UInt32 hole3[5]; /*! 0x6C-0x7C */
176
177 UInt32 ITR0; /*! 0x80 Interrupt Input Register */
178 UInt32 MIR0; /*! 0x84 Mask Interrupt Register */
179 UInt32 MIR_CLEAR0; /*! 0x88 MIR Clear Register */
180 UInt32 MIR_SET0; /*! 0x8C MIR Set Register */
181 UInt32 ISR_SET0; /*! 0x90 Interrupt Set Register */
182 UInt32 ISR_CLEAR0; /*! 0x94 Interrupt Clear Register */
183 UInt32 PENDING_IRQ0; /*! 0x98 Pending IRQ Register */
184 UInt32 PENDING_FIQ0; /*! 0x9C Pending FIQ Register */
185
186 UInt32 ITR1; /*! 0xA0 Interrupt Input Register */
187 UInt32 MIR1; /*! 0xA4 Mask Interrupt Register */
188 UInt32 MIR_CLEAR1; /*! 0xA8 MIR Clear Register */
189 UInt32 MIR_SET1; /*! 0xAC MIR Set Register */
190 UInt32 ISR_SET1; /*! 0xB0 Interrupt Set Register */
191 UInt32 ISR_CLEAR1; /*! 0xB4 Interrupt Clear Register */
192 UInt32 PENDING_IRQ1; /*! 0xB8 Pending IRQ Register */
193 UInt32 PENDING_FIQ1; /*! 0xBC Pending FIQ Register */
194
195 UInt32 ITR2; /*! 0xC0 Interrupt Input Register */
196 UInt32 MIR2; /*! 0xC4 Mask Interrupt Register */
197 UInt32 MIR_CLEAR2; /*! 0xC8 MIR Clear Register */
198 UInt32 MIR_SET2; /*! 0xCC MIR Set Register */
199 UInt32 ISR_SET2; /*! 0xD0 Interrupt Set Register */
200 UInt32 ISR_CLEAR2; /*! 0xD4 Interrupt Clear Register */
201 UInt32 PENDING_IRQ2; /*! 0xD8 Pending IRQ Register */
202 UInt32 PENDING_FIQ2; /*! 0xDC Pending FIQ Register */
203
204 UInt32 ITR3; /*! 0xE0 Interrupt Input Register */
205 UInt32 MIR3; /*! 0xE4 Mask Interrupt Register */
206 UInt32 MIR_CLEAR3; /*! 0xE8 MIR Clear Register */
207 UInt32 MIR_SET3; /*! 0xEC MIR Set Register */
208 UInt32 ISR_SET3; /*! 0xF0 Interrupt Set Register */
209 UInt32 ISR_CLEAR3; /*! 0xF4 Interrupt Clear Register */
210 UInt32 PENDING_IRQ3; /*! 0xF8 Pending IRQ Register */
211 UInt32 PENDING_FIQ3; /*! 0xFC Pending FIQ Register */
212
213 UInt32 ILR[128]; /*! 0x100 thru 0x2FC */
214 };
215
216 extern volatile Intc intc;
217
218 /*!
219 * Exception Context - Register contents at the time of an exception.
220 */
221 struct ExcContext {
222
223 BIOS.ThreadType threadType;
224
225 Ptr threadHandle;
226
227 Ptr threadStack;
228
229
230
231
232 Ptr r0;
233 Ptr r1;
234 Ptr r2;
235 Ptr r3;
236 Ptr r4;
237 Ptr r5;
238 Ptr r6;
239 Ptr r7;
240 Ptr r8;
241 Ptr r9;
242 Ptr r10;
243 Ptr r11;
244 Ptr r12;
245 Ptr sp;
246 Ptr lr;
247 Ptr pc;
248 Ptr psr;
249 }
250
251
252
253 /*! Reset Handler. Default is c_int00 */
254 metaonly config VectorFuncPtr resetFunc;
255
256 /*!
257 * Undefined instruction exception handler.
258 * Default is an internal exception handler.
259 */
260 metaonly config VectorFuncPtr undefinedInstFunc;
261
262 /*!
263 * SWI Handler. Default is internal SWI handler.
264 * Default is an internal exception handler.
265 */
266 metaonly config VectorFuncPtr swiFunc;
267
268 /*!
269 * Prefetch abort exception handler.
270 * Default is an internal exception handler.
271 */
272 metaonly config VectorFuncPtr prefetchAbortFunc;
273
274 /*!
275 * Data abort exception handler.
276 * Default is an internal exception handler.
277 */
278 metaonly config VectorFuncPtr dataAbortFunc;
279
280 /*!
281 * Reserved exception handler.
282 * Default is an internal exception handler.
283 */
284 metaonly config VectorFuncPtr reservedFunc;
285
286 /*! IRQ interrupt handler. Default is internal IRQ dispatcher */
287 metaonly config VectorFuncPtr irqFunc;
288
289 /*! FIQ interrupt handler. Default is internal FIQ dispatcher */
290 metaonly config VectorFuncPtr fiqFunc;
291
292 /*!
293 * Enable full exception decoding
294 *
295 * When this is enabled, the exception handler will fully
296 * decode an exception and dump the registers to the
297 * system console.
298 */
299 metaonly config Bool enableException = false;
300
301 /*!
302 * FIQ stack pointer. Default = null.
303 * (Indicates that stack is to be created internally)
304 */
305 config Ptr fiqStack = null;
306
307 /*!
308 * FIQ stack size in MAUs.
309 * Default is 1024 bytes.
310 */
311 metaonly config SizeT fiqStackSize = 1024;
312
313 /*!
314 * Memory section used for FIQ stack
315 * Default is null.
316 */
317 metaonly config String fiqStackSection = null;
318
319 /*!
320 * Exception stack pointer. Default = null.
321 * (Indicates that stack is to be created internally)
322 */
323 config Ptr excStack = null;
324
325 /*!
326 * Exception stack size in MAUs.
327 * Default is 1024 bytes.
328 */
329 metaonly config SizeT excStackSize = 1024;
330
331 /*!
332 * Memory section used for Exception stack
333 * Default is null.
334 */
335 metaonly config String excStackSection = null;
336
337 /*! Initial MIR0 Interrupt Mask. Default is 0xffffffff */
338 config Bits32 mir0Mask = 0xffffffff;
339
340 /*! Initial MIR1 Interrupt Mask. Default is 0xffffffff */
341 config Bits32 mir1Mask = 0xffffffff;
342
343 /*! Initial MIR2 Interrupt Mask. Default is 0xffffffff */
344 config Bits32 mir2Mask = 0xffffffff;
345
346 /*! Initial MIR3 Interrupt Mask. Default is 0xffffffff */
347 config Bits32 mir3Mask = 0xffffffff;
348
349 /*!
350 * Error raised when an attempt is made to create a Hwi
351 * that has already been created.
352 */
353 config Error.Id E_alreadyDefined = {
354 msg: "E_alreadyDefined: Hwi already defined, intnum: %d"
355 };
356
357 /*!
358 * Error raised when Hwi handle referenced in Hwi_delete()
359 * is not found in the Hwi dispatch table
360 */
361 config Error.Id E_handleNotFound = {
362 msg: "E_handleNotFound: Hwi handle not found: 0x%x"
363 };
364
365 /*!
366 * Error raised when an undefined interrupt has fired.
367 */
368 config Error.Id E_undefined = {
369 msg: "E_undefined: Hwi undefined, intnum: %d"
370 };
371
372 /*!
373 * Error raised if an attempt is made to create a Hwi
374 * with an interrupt number greater than NUM_INTERRUPTS - 1.
375 */
376 config Error.Id E_badIntNum = {
377 msg: "E_badIntNum, intnum: %d is out of range"
378 };
379
380 /*!
381 * Error raised when an exception occurs
382 */
383 config Error.Id E_excMin = {
384 msg: "E_exception: pc = 0x%08x, lr = 0x%08x."
385 };
386
387 /*!
388 * Issued just prior to Hwi function invocation (with interrupts disabled)
389 */
390 config Log.Event LM_begin = {
391 mask: Diags.USER1 | Diags.USER2,
392 msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
393 };
394
395 /*!
396 * Issued just after return from Hwi function (with interrupts disabled)
397 */
398 config Log.Event LD_end = {
399 mask: Diags.USER2,
400 msg: "LD_end: hwi: 0x%x"
401 };
402
403
404
405
406 /*!
407 * ======== disable ========
408 */
409 @Macro
410 override UInt disable();
411
412 /*!
413 * ======== enable ========
414 */
415 @Macro
416 override UInt enable();
417
418 /*!
419 * ======== restore ========
420 */
421 @Macro
422 override Void restore(UInt key);
423
424 /*!
425 * ======== inUseMeta ========
426 * @_nodoc
427 * Check for Hwi already in use.
428 * For internal SYS/BIOS use only.
429 * Should be called prior to any internal Hwi.create().
430 *
431 * @param(intNum) interrupt number
432 */
433 metaonly Bool inUseMeta(UInt intNum);
434
435 /*!
436 * ======== getHandle ========
437 * Returns Hwi_Handle associated with intNum
438 *
439 * @param(intNum) interrupt number
440 */
441 @DirectCall
442 Handle getHandle(UInt intNum);
443
444 /*!
445 * ======== enableFIQ ========
446 * Enable FIQ interrupts.
447 *
448 * @b(returns) previous FIQ interrupt enable/disable state
449 */
450 @DirectCall
451 UInt enableFIQ();
452
453 /*!
454 * ======== disableFIQ ========
455 * Disable FIQ interrupts.
456 *
457 * @b(returns) previous FIQ interrupt enable/disable state
458 */
459 @DirectCall
460 UInt disableFIQ();
461
462 /*!
463 * ======== restoreFIQ ========
464 * Restore FIQ interrupts.
465 *
466 * @param(key) enable/disable state to restore
467 */
468 @DirectCall
469 Void restoreFIQ(UInt key);
470
471 /*!
472 * ======== enableIRQ ========
473 * Enable IRQ interrupts.
474 *
475 * @param(key) enable/disable state to restore
476 */
477 @DirectCall
478 UInt enableIRQ();
479
480 /*!
481 * ======== disableIRQ ========
482 * Disable IRQ interrupts.
483 *
484 * @b(returns) previous IRQ interrupt enable/disable state
485 */
486 @DirectCall
487 UInt disableIRQ();
488
489 /*!
490 * ======== restoreIRQ ========
491 * Restore IRQ interrupts.
492 *
493 * @param(key) enable/disable state to restore
494 */
495 @DirectCall
496 Void restoreIRQ(UInt key);
497
498 /*!
499 * ======== disableMIR0 ========
500 * Disable specific interrupts.
501 *
502 * Disables specific interrupts by setting the bits specified by
503 * mask in the Mask Interrupts Register (MIR).
504 *
505 * @param(mask) bitmask of interrupts to disable
506 * @b(returns) previous MIR0 settings bitmask
507 */
508 @DirectCall
509 Bits32 disableMIR0(Bits32 mask);
510 @DirectCall
511 Bits32 disableMIR1(Bits32 mask);
512 @DirectCall
513 Bits32 disableMIR2(Bits32 mask);
514 @DirectCall
515 Bits32 disableMIR3(Bits32 mask);
516
517 /*!
518 * ======== enableMIR ========
519 * Enable specific interrupts.
520 *
521 * Enables specific interrupts by clearing the bits specified by
522 * mask in the Mask Interrupts Register (MIR).
523 *
524 * @param(mask) bitmask of interrupts to enable
525 * @b(returns) previous MIR settings bitmask
526 */
527 @DirectCall
528 Bits32 enableMIR0(Bits32 mask);
529 @DirectCall
530 Bits32 enableMIR1(Bits32 mask);
531 @DirectCall
532 Bits32 enableMIR2(Bits32 mask);
533 @DirectCall
534 Bits32 enableMIR3(Bits32 mask);
535
536 /*!
537 * ======== restoreMIR0 ========
538 * Restore maskable interrupts to the state they were in
539 * when either disableMIR0() or enableMIR0() was called.
540 *
541 * Simply writes mask to the MIR register.
542 *
543 * @param(mask) bitmask of interrupts to restore
544 * @b(returns) previous MIR0 settings bitmask
545 */
546 @DirectCall
547 Bits32 restoreMIR0(Bits32 mask);
548 @DirectCall
549 Bits32 restoreMIR1(Bits32 mask);
550 @DirectCall
551 Bits32 restoreMIR2(Bits32 mask);
552 @DirectCall
553 Bits32 restoreMIR3(Bits32 mask);
554
555 /*!
556 * ======== setPriority ========
557 * Set an interrupt's priority.
558 *
559 * Not an instance function so that it can be used
560 * with non-dispatched interrupts.
561 *
562 * @param(intNum) ID of interrupt
563 * @param(priority) priority
564 */
565 @DirectCall
566 Void setPriority(UInt intNum, UInt priority);
567
568 /*!
569 * ======== setType ========
570 * Set an interrupt's type (FIQ/IRQ).
571 *
572 * Not an instance function so that it can be used
573 * with non-dispatched interrupts.
574 *
575 * @param(intNum) ID of interrupt
576 * @param(type) type = FIQ/IRQ
577 */
578 @DirectCall
579 Void setType(UInt intNum, Type type);
580
581 instance:
582
583 /*! Interrupt type (IRQ/FIQ). Default is IRQ. */
584 config Type type = Type_IRQ;
585
586 587 588 589 590 591 592 593 594 595 596
597 override config Int priority = -1;
598
599 /*! The interrupt controller is designed for priority based interrupts */
600 override config IHwi.MaskingOption maskSetting = IHwi.MaskingOption_LOWER;
601
602 /*!
603 * ======== reconfig ========
604 * Reconfigure a dispatched interrupt.
605 */
606 @DirectCall
607 Void reconfig(FuncPtr fxn, const Params *params);
608
609 internal:
610
611 612 613 614 615 616
617 config UInt (*swiDisable)();
618 config Void (*swiRestoreHwi)(UInt);
619 config UInt (*taskDisable)();
620 config Void (*taskRestoreHwi)(UInt);
621
622
623 Void init();
624
625
626 Void dispatchIRQ();
627
628
629 Void dispatchIRQC(Irp irp);
630
631
632 Void dispatchFIQC();
633
634
635 Void nonPluggedHwiHandler(UArg arg);
636
637 /*!
638 * const array to hold all HookSet objects.
639 */
640 config HookSet hooks[length] = [];
641
642 /*! Meta World Only Hwi Configuration Object. */
643 metaonly struct InterruptObj {
644 Bool used;
645 FuncPtr fxn;
646 };
647
648 /*!
649 * Meta-only array of interrupt objects.
650 * This meta-only array of Hwi config objects is initialized
651 * in Hwi.xs:module$meta$init().
652 */
653 metaonly config InterruptObj interrupt[NUM_INTERRUPTS];
654
655 struct Instance_State {
656 Type type;
657 UInt priority;
658 UArg arg;
659 FuncPtr fxn;
660 Irp irp;
661 Ptr hookEnv[];
662 };
663
664 struct Module_State {
665 Bits32 mir0Mask;
666 Bits32 mir1Mask;
667 Bits32 mir2Mask;
668 Bits32 mir3Mask;
669 UInt spuriousInts;
670 UInt lastSpuriousInt;
671 UInt irp;
672 Char *taskSP;
673
674
675 Char *isrStack;
676 Ptr isrStackBase;
677 Ptr isrStackSize;
678 Char fiqStack[];
679 SizeT fiqStackSize;
680 Hwi.Object nonPluggedHwi;
681 Handle dispatchTable[NUM_INTERRUPTS];
682
683 };
684 }
685
686 687 688 689
690