1 /*
2 * Copyright (c) 2011, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * */
32 /*
33 * ======== ICache.xdc ========
34 *
35 *
36 */
37
38 /*!
39 * ======== ICache ========
40 * Cache Interface
41 */
42
43 interface ICache
44 {
45 /*! Lists of bitmask cache types */
46 enum Type {
47 Type_L1P = 0x1, /*! Level 1 Program cache */
48 Type_L1D = 0x2, /*! Level 1 Data cache */
49 Type_L1 = 0x3, /*! Level 1 caches */
50 Type_L2P = 0x4, /*! Level 2 Program cache */
51 Type_L2D = 0x8, /*! Level 2 Data cache */
52 Type_L2 = 0xC, /*! Level 2 caches */
53 Type_ALLP = 0x5, /*! All Program caches */
54 Type_ALLD = 0xA, /*! All Data caches */
55 Type_ALL = 0x7fff /*! All caches */
56 };
57
58 /*!
59 * ======== enable ========
60 * Enables all cache(s)
61 *
62 * @param(type) bit mask of Cache type
63 */
64 @DirectCall
65 Void enable(Bits16 type);
66
67 /*!
68 * ======== disable ========
69 * Disables the 'type' cache(s)
70 *
71 * @param(type) bit mask of Cache type
72 */
73 @DirectCall
74 Void disable(Bits16 type);
75
76 /*!
77 * ======== inv ========
78 * Invalidate the range of memory within the specified starting
79 * address and byte count. The range of addresses operated on
80 * gets quantized to whole cache lines in each cache. All lines
81 * in range are invalidated for all the 'type' caches.
82 *
83 * @param(blockPtr) start address of range to be invalidated
84 * @param(byteCnt) number of bytes to be invalidated
85 * @param(type) bit mask of Cache type
86 * @param(wait) wait until the operation is completed
87 */
88 @DirectCall
89 Void inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
90
91 /*!
92 * ======== wb ========
93 * Writes back a range of memory from all cache(s)
94 *
95 * Writes back the range of memory within the specified starting
96 * address and byte count. The range of addresses operated on
97 * gets quantized to whole cache lines in each cache. All lines
98 * within the range are left valid in the 'type' caches and the data
99 * within the range will be written back to the source memory.
100 *
101 * @param(blockPtr) start address of range to be invalidated
102 * @param(byteCnt) number of bytes to be invalidated
103 * @param(type) bit mask of Cache type
104 * @param(wait) wait until the operation is completed
105 */
106 @DirectCall
107 Void wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
108
109 /*!
110 * ======== wbInv ========
111 * Writes back and invalidates the range of memory within the
112 * specified starting address and byte count. The range of
113 * addresses operated on gets quantized to whole cache lines in
114 * each cache. All lines within the range are written back to the
115 * source memory and then invalidated for all 'type' caches.
116 *
117 * @param(blockPtr) start address of range to be invalidated
118 * @param(byteCnt) number of bytes to be invalidated
119 * @param(type) bit mask of Cache type
120 * @param(wait) wait until the operation is completed
121 */
122 @DirectCall
123 Void wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
124
125 /*!
126 * ======== wbAll ========
127 * Write back all caches
128 *
129 * Perform a global write back. There is no effect on program cache.
130 * All data cache lines are left valid.
131 */
132 @DirectCall
133 Void wbAll();
134
135 /*!
136 * ======== wbInvAll ========
137 * Write back invalidate all caches
138 *
139 * Performs a global write back and invalidate. All cache lines
140 * are written out to physical memory and then invalidated.
141 */
142 @DirectCall
143 Void wbInvAll();
144
145 /*!
146 * ======== wait ========
147 * Wait for a previous cache operation to complete
148 *
149 * Wait for the cache wb/wbInv/inv operation to complete. A cache
150 * operation is not truly complete until it has worked its way
151 * through all buffering and all memory writes have landed in the
152 * source memory.
153 */
154 @DirectCall
155 Void wait();
156
157 }
158
159 /*
160 * @(#) ti.sysbios.interfaces; 2, 0, 0, 0,451; 1-20-2011 12:28:39; /db/vtree/library/trees/avala/avala-o26x/src/ xlibrary
161 162 */
163