Benchmark | Cycles | |
Interrupt latency | 82 | (1) |
Hwi_enable | 10 | |
Hwi_disable | 14 | |
Hwi dispatcher prolog | 118 | |
Hwi dispatcher epilog | 174 | |
Hwi dispatcher | 282 | |
Hardware Interrupt to Blocked Task | 535 | |
Hardware Interrupt to Software Interrupt | 379 | |
Swi_enable | 86 | |
Swi_disable | 11 | |
Post Software Interrupt Again | 42 | |
Post Software Interrupt without Context Switch | 146 | |
Post Software Interrupt with Context Switch | 235 | |
Create a New Task without Context Switch | 1426 | |
Set a Task Priority without a Context Switch | 235 | |
Task_yield | 242 | |
Post Semaphore, No Waiting Task | 54 | |
Post Semaphore No Task Switch | 233 | |
Post Semaphore with Task Switch | 306 | |
Pend on Semaphore, No Context Switch | 69 | |
Pend on Semaphore with Task Switch | 296 | |
Clock_getTicks | 10 |
(1) The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.