| Benchmark | Cycles | |
| Interrupt latency | 82 | (1) |
| Hwi_enable | 11 | |
| Hwi_disable | 15 | |
| Hwi dispatcher prolog | 110 | |
| Hwi dispatcher epilog | 166 | |
| Hwi dispatcher | 266 | |
| Hardware Interrupt to Blocked Task | 497 | |
| Hardware Interrupt to Software Interrupt | 350 | |
| Swi_enable | 88 | |
| Swi_disable | 11 | |
| Post Software Interrupt Again | 46 | |
| Post Software Interrupt without Context Switch | 131 | |
| Post Software Interrupt with Context Switch | 208 | |
| Create a New Task without Context Switch | 1402 | |
| Set a Task Priority without a Context Switch | 213 | |
| Task_yield | 215 | |
| Post Semaphore, No Waiting Task | 63 | |
| Post Semaphore with Task Switch | 284 | |
| Pend on Semaphore, No Context Switch | 79 | |
| Pend on Semaphore with Task Switch | 285 | |
| Clock_getTicks | 10 |
(1) The M3 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.