Version: DaVinci EVM in L1 Memory

benchmarks @(#)DSP/BIOS_Benchmarks 5,2,4,5 10-02-2007 (bench-h11)

Timing Benchmarks

BenchmarkCycles
Interrupt latency97
HWI_enable12
HWI_disable14
HWI_dispatch: Interrupt prolog for calling C function80
HWI_dispatch: Interrupt epilog following C function call70
SEM_ipost: Hardware interrupt to blocked task581
SWI_post: Hardware interrupt to software interrupt201
SWI_enable62
SWI_disable21
SWI_post: Post software interrupt again28
SWI_post: Post software interrupt, no context switch57
SWI_post: Post software interrupt, context switch122
TSK_enable86
TSK_disable45
TSK_create: Create a task, no context switch666
TSK_create: Create a task, context switch765
TSK_delete426
TSK_setpri: Set a task priority, no context switch282
TSK_setpri: Lower the current task own priority, context switch372
TSK_setpri: Raise a ready task priority, context switch372
TSK_yield228
SEM_post: Post a semaphore, no waiting task28
SEM_post: Post a semaphore, no context switch181
SEM_post: Post a semaphore, context switch257
SEM_pend: Pend on a semphore, no context switch19
SEM_pend: Pend on a semphore, context switch236
MBX_post: Post a mailbox, no tasks waiting112
MBX_post: Post a mailbox, no context switch265
MBX_post: Post a mailbox, context switch417
MBX_pend: Pend on a mailbox, no context switch112
MBX_pend: Pend on a mailbox, context switch246
LCK_post: Post a lock, no ownership relinquishment21
LCK_post: Post a lock, no context switch42
LCK_post: Post a lock, context switch285
LCK_pend: Pend on a self-owned lock30
LCK_pend: Pend on a lock, no context switch50
LCK_pend: Pend on a lock, context switch252
CLK_gethtime13
CLK_getltime19
LOG_event21
LOG_printf29
STS_add16
STS_delta19
STS_set13
MEM_alloc: Memory allocated on first block202
MEM_alloc: Memory allocated on second block214
MEM_alloc: Memory allocated on third block226
MEM_alloc: Memory allocated on fourth block238
MEM_free: Memory coalesces no block220
MEM_free: Memory coalesces one block240
MEM_free: Memory coalesces two blocks240
PIP_alloc97
PIP_free95
PIP_get97
PIP_put97
PIP_peek22
QUE_dequeue14
QUE_empty10
QUE_enqueue11
QUE_get19
QUE_insert10
QUE_put15
QUE_remove15
MSGQ_alloc111
MSGQ_put53
MSGQ_get with messages56
MSGQ_get with no messages74
MSGQ_free57
Note: Interrupt latency for DM644x rev 1.x is 126 cpu clock cycles. This is due to the workaround for IDMA0 problem.