DSP/BIOS v5.31.08 Release Notes

 

Last updated:  10 Jul 2007

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Known Issues", "Fixed In This Release", and "Validation Info".   

Check the following web site for updates: https://www-a.ti.com/downloads/sds_support/targetcontent/bios/index.html

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package (updated)
  DSP/BIOS Kernel Benchmarks
  XDC Tools (Tconf) Package (updated)
  DSP/BIOS Platforms (updated)
  DSP/BIOS Examples (updated)
  Real Time Data Exchange (RTDX)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support)
  DSP/BIOS Help Files
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD)
  DSP/BIOS Graphical Configuration Tool (Gconf)

General Information

DSP/BIOS 5.31.08 is an all ISA release and can be used with CCS 3.2, CCS 3.3 or later. This will be installed in <installdir>/bios_5_31_08.

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.31.08

Device Support

     
  Devices Supported* Runtime model
 

*BIOS Configuration DeviceName listed

 
     
28xx Devices    
  F2801
F2806
F2808
F2810
F2811
F2812
 
Large model
     
54xx Devices    
 
5402
5402A
5409A
5416
5470
5471
5405
 
Near and Far model supported
     
55xx Devices    
 

5501
5502
5503
5507
5509A
DA255
5510
5510A
5561

 

Large model on Laijin 2.x core devices

Note: 55xx small model support has been dropped starting with BIOS 5.10

 

5903 (OMAP)
5905
(OMAP)

5910 (OMAP)
5912 (OMAP)

5948 (OMAP)
5946 (OMAP)
5944 (OMAP)


1035 (OMAP)
1510 (OMAP)
1610 (OMAP)
1710 (OMAP)
2320 (OMAP)
2420 (OMAP)
 

TNETV1055

Large model for 55xx DSP side of Heterogeneous multi processors (OMAP: ARM + 55xx DSP, Titan: MIPS + 55xx DSP)

Large and Huge model for 55xx DSP on Laijin 2.x/3.x, such as OMAP1710, OMAP2420

Note: 55xx small model support has been dropped starting with BIOS 5.10

     
62xx Devices    
  Not Supported: C6201
6202
6203
6204
6205
6211

 

Big and Little Endian
     
67xx Devices    
6701
6711
6711 - 250
6712
6713
6713 - 300
 

 

Big and Little Endian
     
64xx Devices    
  6410
6411
6412
6413
6414
6415
6416
6418
DRI300
DM640
DM641
DM642
Big and Little Endian
     
64P  Devices    

DM420
DM415
DM425
DM426

DM647

DM648

 

DM6431
DM6433
DM6435

DM6437
DM6443
DM6446

 

6421
6424
6452
6455
6454

 

TCI6482

TCI6486
TCI6487
TCI6488

 

DRA442
DRA446

 

2430 (OMAP)
3430 (OMAP)

TNETV2685

Big and Little Endian
     
67P  Devices    
  6727

DA705
DA707
DA710

Little Endian
     
IAG Devices    
  DM270
DM310
DM320

DM420
DA300
DA295

 

Known Issues

    Please check the following link for additional information when upgrading from 4.90 to 5.x -- Knowledge base with known 4.90 to 5.x upgrade issues

   OMAP2430/3430 HWI/WUGEN API Documentation -- The new HWI/WUGEN APIs are not documented in the BIOS API Guide.  This is tracked by SDSCM00016107 which contains documentation for each API.

    PWRM/3430 Documentation Update  --  SDSCM00014096: When the IVA MMU is enabled and PWRM is enabled, the base addresses of the support modules must be mapped into the IVA MMU and BIOS must be configured with the respective virtual addresses using the following PWRM configuration properties:

    CM_BASEADDR
    IVAMMU_BASEADDR
    PRM_BASEADDR
    SCM_BASEADDR
 
    Base address of Clock Manager (CM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Clock Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.
 
    Tconf Name: CM_BASEADDR
    Type: Address
    Example: bios.PWRM.CM_BASEADDR = 0x12004000
 
    Base address of IVA MMU. When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the IVA MMU. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.
 
    Tconf Name: IVAMMU_BASEADDR
    Type: Address
    Example: bios.PWRM.IVAMMU_BASEADDR = 0x12005000
 
    Base address of Power & Reset Manager (PRM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Power & Reset Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.
 
    Tconf Name: PRM_BASEADDR
    Type: Address
    Example: bios.PWRM.PRM_BASEADDR = 0x12006000
 
    Base address of System Control Module (SCM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the System Control Module. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.
 
    Tconf Name: SCM_BASEADDR
    Type: Address
    Example: bios.PWRM.SCM_BASEADDR = 0x12007000
 
 
    SDSCM00014100: Incorrect code example for setting wakeup event in SPRAA98. There is a typo in the DSP/BIOS Power Management AppNote document (SPRAA98). Its in a code example on how to set the wakeup event. The index values for sleepArgs should start at 0, not at 1.
 
    Incorrect version (page 28):
 
    sleepArgs[1] = 0xFFFFFFBF; /* enable GP timer 5 as wakeup */
    sleepArgs[2] = 0x0000FFFF; /* no wakeups via WUGEN_MEVT1 */
    sleepArgs[3] = 0x000FFFFF; /* no wakeups via WUGEN_MEVT2 */
    sleepArgs[4] = 0x00000001; /* no wakeups via WUGEN_MEVT3 */
 
    Correct version:
 
    sleepArgs[0] = 0xFFFFFFBF; /* enable GP timer 5 as wakeup */
    sleepArgs[1] = 0x0000FFFF; /* no wakeups via WUGEN_MEVT1 */
    sleepArgs[2] = 0x000FFFFF; /* no wakeups via WUGEN_MEVT2 */
    sleepArgs[3] = 0x00000001; /* no wakeups via WUGEN_MEVT3 */
 
    SDSCM00018594: SPRAA98 needs updating with pwrm changes for BIOS 5.31.08 release. The document spraa98 needs updating to reflect the recent changes made to pwrm for the BIOS 5.31.08 release. These updates include the following:

    The PWRM_CPULoadInfo structure has changed; the field "idleCycles" has been replaced with "busyCycles". This field tracks the number of cycles the CPU was busy for the given load slot.
 
    typedef struct PWRM_CPULoadInfo {
        Uns busyCycles;  /* used to be idleCycles *.
        Uns totalCycles;
        Uns timeStamp;
    } PWRM_CPULoadInfo;
    New load APIs have been added to start/stop load monitoring. When using timer based load monitoring, the resource tracking will automatically track a dependency on the timer. Using the CPU load monitoring start/stop APIs will call set/release dependency on the timer. This allows for notification to the client which can then start/stop the interface and functional clocks on the timer.
 
    extern PWRM_Status PWRM_startCPULoadMonitoring(Void);
    extern PWRM_Status PWRM_stopCPULoadMonitoring(Void);
 
    The CPU load monitoring now supports a timer as an external timebase. This allows the GEM to be placed in standby mode while still performing CPU load monitoring. The external timer is used to wake the GEM when it is time to finalize the current load slot.
 
    Here are the configuration properties to support the new timer based load monitoring.
 
    To use timer based CPU load monitoring, set the USETIMER property to 1. Note, you must first set USECLKPRD to 0 in order to select the timer configuration (bios.PWRM.USECLKPRD = 0).
 
    Tconf Name: USETIMER
    Type: Boolean
    Example: bios.PWRM.USETIMER = 1
 
    Select which timer to use as the time base for CPU load monitoring. You man choose from timer 5, 6, 7, 8. Note, you cannot use the same timer which is being used for the BIOS clock.
 
    Tconf Name: TIMERID
    Type: String
    Example: bios.PWRM.TIMERID = "Timer 7"
 
    Base address of timer. When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the timer. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address. If the IVA MMU is disabled, the timer physical address must be specified.
 
    Tconf Name: TIMERBASEADDR
    Type: Address
    Example: bios.PWRM.TIMERBASEADDR = 0x4903C000
 
    Timer input clock speed. The timer input clock speed must be specified. It is specified in KHz.
 
    Tconf Name: TIMERINPUTCLK
    Type: Unsigned
    Example: bios.PWRM.TIMERINPUTCLK = 19200
 
    Timer period. Specify the period at which the timer should finalize the CPU load monitoring slots. The period is specified in milliseconds.
 
    Tconf Name: TIMERPERIOD
    Type: Unsigned
    Example: bios.PWRM.TIMERINPUTCLK = 10
 
    Timer interrupt. Specify which CPU interrupt the timer should be routed to.
 
    Tconf Name: TIMERINTR
    Type: HWI
    Example: bios.PWRM.TIMERINTR = prog.get("HWI_INT15")
 
    A new sleep mode has been added to PWRM_sleepDSP to put the GEM into standby mode. The sleepCode parameter is PWRM_STANDBY. The sleepArg is the same as for PWRM_RETENTION and PWRM_HIBERNATE sleep modes. This sleep mode puts the GEM into standby mode. This is a fast, low latency, power saving mode. In this mode, all IVA2 clocks are stopped but power remains on. The GEM is taken out of standby mode by a wakup event triggered by an interrupt through the WUGEN.

    Davinci 1.x IDMA0 problem workaround -- A custom version of the HWI dispatcher was created to  work around an IDMA0/MMR problem in rev 1.x DM644x devices (see SPRZ241 - "TMS320DM6446 Digital Media System-on-chip Silicon Errata" for more information about this errata).  This errata is only present in Rev 1.x DM644x devices and is not present on other 64x+ devices.
 The HWI dispatcher has been updated to poll the IDMA0 status register and wait for IDMA0 transfer to complete before calling the actual ISR.  This will ensure that the ISR will not reference an MMR register while the IDMA0 is active.  This will also ensure that an asynchronous task switch will not occur while the IDMA0 is active.  This may affect interrupt response time, but should not be a problem in most applications since IDMA0 jobs are usually fairly short.  This workaround is only supported by the HWI dispatcher (the HWI_enter/exit macros do not contain the workaround).
 A hidden configuration parameter (bios.GBL.USEIDMA0DISPATCHER) is used to select this alternate version of the dispatcher.  This parameter has default value 'true' for DM644x and DM42x configurations.  This parameter has default value 'false' for all other 64x+ configurations.  The user can set this parameter to 'false' if they do not want this workaround used in their Davinci applications (e.g., if their application is not using IDMA0 and/or they know that that their ISRs do not reference MMR registers).

    Memory heap issue when updating  existing configuration files -- Prior versions of the configuration tool allowed for an inconsistent memory heap configuration.   The tool allowed users to enable heaps when no heaps were actually configured and the default for bios.MEM.MALLOCSEG and bios.MEM.SEGZERO were still set to 'MEM_NULL'.  This was causing problems in applications since malloc() and MEM_alloc() were failing even when user thought they had configured BIOS for dynamic memory allocation.  The configuration tool is now checking to make sure that configurations that have heaps also have bios.MEM.MALLOCSEG and bios.MEM.SEGZERO set to a valid heap.  Update from existing projects might yield an error message.  The work around is to either remove the 'bios.enableMemoryHeaps(prog);' line from your configuration, or to add a heap and set bios.MEM.MALLOCSEG and bios.MEM.SEGZERO accordingly.  See the ti/bios/examples/common/evmDM6446_common.tci file (or others) for an example of how to do this.

   Gconf uses wrong parameters when more than one pjt is opened and they share the same .tcf file -- When more than one CCS project (.pjt file) share the same .tcf file, and two or more of the projects are opened in CCS, opening a .tcf from one of the projects will launch GConf using the DspBiosBuilder builder parameters defined for the most recently opened project. This may result in incorrect base seed properties and import file paths in the .tcf file being edited. To workaround, do not share .tcf files between projects. This is tracked by SDSCM00003834

  BIOS RTA has problems reading data in stop mode for some 64x+ devices -- Currently, stop mode reads will only work for DaVinci. This is tracked by SDSCM00010400

    DSP/BIOS examples that are using RTA halt when run every other time on DSK5510/DSK5509A via XDS560. This is tracked by SDSCM00005820.

    CCS window closes on refreshing KOV Window when it receives illegal values -- KOV will crash if Module Objects have illegal values. For e.g if a dynamic task has a bad name, KOV will try to print the illegal name and crash. This is tracked by SDSCM00006694.   

    KOV window shows wrong names for dynamic objects -- This is tracked by SDSCM00007151.

    KOV displays wrong names for memory sections -- This is tracked by SDSCM00004917.

    Incorrect platform name in Tconf User's Guide in "Create New Platform" section -- The spru0007h.pdf document contains the correct instructions for creating a new platform using the Tconf's User's Guide, the help files were not updated to reflect the same naming convention. This is tracked by SDSCM00003471.

    RTDX tutorial examples do not all execute as expected  when run on TCI6482 simulator little endian -- This is tracked by SDSSCM00010736.

    RTDX Hot-Connect does not work for C64P -- This is tracked by SDSSCM00011954.

    RTA (VBD) crash after lots of disconnects and connects -- This is tracked by SDSSCM00012471.

    DSP/BIOS RTA Control Panel does not update values correctly when using comma decimal separator in Windows -- The RTA Control Panel does not work as expected when using Windows Regional Settings where ',' is used instead of '.' for the decimal separator.  Only workaround is to use Regional Settings where '.' is the decimal separator, or use default 1 second update rate.  This is tracked by SDSCM00017755.

Fixed In This Release

The following bugs and enhancements have been fixed in this release.  These are also listed in the sub-component release notes, but provided here for convenience.


id Headline
SDSCM00018359 C55_l2EnableMIR1/DisableMIR1 (and others?) should be in .bios section
SDSCM00018346 Timer frequency on DM6467 shoud be set to DSP CPU frequency / 4
SDSCM00018213 add C6428.tci and bios_6428.tci files to ti/catalog/c6000 and ti/bios/config
SDSCM00018212 add platform file for evmTNETV2685
SDSCM00018175 Enhanced CPU load monitoring support and PWRM update
SDSCM00018162 need to review/update platform files for evmDM6467 after wakeup
SDSCM00018161 need platform files for evm6452
SDSCM00017824 CPU load for DRA442/DRA446 is incorrect.
SDSCM00017823 The real cpu load is incorrect in the BIOS stairstep example for fast 64P platforms
SDSCM00015095 Platform file missing for OMAP3430 devices


Validation Information

Codegen versions used in BIOS 5.31.05 product validation. See kernel release notes for the compiler versions used to build the target content.

ISA

Compiler version(s)

c6x v6.0.8
c55x v3.3.2
c54x v4.1.0
c28x v4.1.3

 

Deprecation Notice

 

Deprecated DSP/BIOS APIs: Some DSP/BIOS APIs are being deprecated and will no longer be supported in the next major release of DSP/BIOS.

These APIs are still supported in DSP/BIOS 5.31.08 and will be supported in any patch releases or minor enhancements to DSP/BIOS 5.31.

 

The deprecated APIs are:

 

All APIs associated with the DEV driver interface. Developers are recommended to use the IOM driver interface.

 

DEV_createDevice

DEV_deleteDevice

DEV_match

Dxx_close

Dxx_ctrl

Dxx_idle

Dxx_init

Dxx_issue

Dxx_open

Dxx_ready

Dxx_reclaim

DGN Driver

DGS Driver

DHL Driver

 

All APIs associated with the PIP module. Developers are recommended to use the SIO module.

 

PIP_alloc

PIP_free

PIP_get

PIP_getReaderAddr

PIP_getReaderNumFrames

PIP_getReaderSize

PIP_getWriterAddr

PIP_getWriterNumFrames

PIP_getWriterSize

PIP_peek

PIP_put                                                                                        

PIP_reset

PIP_setWriterSize

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_31.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.31.00.01 with directory  bios_5_31_00_01) and the final release will be bios_5_31 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.31.03 with directory bios_5_31_03.  

Point releases where new features such as additional device support are added, increment the minor digits and reset the patch counter (i.e., the patch counter is set to zero and removed from the directory qualifier).  For example, if the current BIOS version is 5.31.03, a subsequent point release would be 5.32. 



DSP/BIOS v5.31.07 Release Notes

 

Last updated:  29 May 2007

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Known Issues", "Fixed In This Release", and "Validation Info".   

Check the following web site for updates: https://www-a.ti.com/downloads/sds_support/targetcontent/bios/index.html

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package (updated)
  DSP/BIOS Kernel Benchmarks
  XDC Tools (Tconf) Package (updated)
  DSP/BIOS Platforms (updated)
  DSP/BIOS Examples (updated)
  Real Time Data Exchange (RTDX)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support)
  DSP/BIOS Help Files
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD)
  DSP/BIOS Graphical Configuration Tool (Gconf)

General Information

DSP/BIOS 5.31.07 is an all ISA release and can be used with CCS 3.2, CCS 3.3 or later. This will be installed in <installdir>/bios_5_31_07.

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.31.07

Device Support

     
  Devices Supported* Runtime model
 

*BIOS Configuration DeviceName listed

 
     
28xx Devices    
  F2801
F2806
F2808
F2810
F2811
F2812
 
Large model
     
54xx Devices    
 
5402
5402A
5409A
5416
5470
5471
5405
 
Near and Far model supported
     
55xx Devices    
 

5501
5502
5503
5507
5509A
DA255
5510
5510A
5561

 

Large model on Laijin 2.x core devices

Note: 55xx small model support has been dropped starting with BIOS 5.10

 

5903 (OMAP)
5905
(OMAP)

5910 (OMAP)
5912 (OMAP)

5948 (OMAP)
5946 (OMAP)
5944 (OMAP)


1035 (OMAP)
1510 (OMAP)
1610 (OMAP)
1710 (OMAP)
2320 (OMAP)
2420 (OMAP)
 

TNETV1055

Large model for 55xx DSP side of Heterogeneous multi processors (OMAP: ARM + 55xx DSP, Titan: MIPS + 55xx DSP)

Large and Huge model for 55xx DSP on Laijin 2.x/3.x, such as OMAP1710, OMAP2420

Note: 55xx small model support has been dropped starting with BIOS 5.10

     
62xx Devices    
  Not Supported: C6201
6202
6203
6204
6205
6211

 

Big and Little Endian
     
67xx Devices    
6701
6711
6711 - 250
6712
6713
6713 - 300
 

 

Big and Little Endian
     
64xx Devices    
  6410
6411
6412
6413
6414
6415
6416
6418
DRI300
DM640
DM641
DM642
Big and Little Endian
     
64P  Devices    

DM420
DM415
DM425
DM426

DM647

DM648

 

DM6431
DM6433
DM6435

DM6437
DM6443
DM6446

 

6421
6424
6452
6455
6454

 

TCI6482

TCI6486
TCI6487
TCI6488

 

DRA442
DRA446

 


2430 (OMAP)
3430 (OMAP)

Big and Little Endian
     
67P  Devices    
  6727

DA705
DA707
DA710

Little Endian
     
IAG Devices    
  DM270
DM310
DM320

DM420
DA300
DA295

 

Known Issues

    Please check the following link for additional information when upgrading from 4.90 to 5.x -- Knowledge base with known 4.90 to 5.x upgrade issues

   OMAP2430/3430 HWI/WUGEN API Documentation -- The new HWI/WUGEN APIs are not documented in the BIOS API Guide.  This is tracked by SDSCM00016107 which contains documentation for each API.

    PWRM/3430 Documentation Update -- When the IVA MMU is enabled and PWRM is enabled, the base addresses of the support modules must be mapped into the IVA MMU and BIOS must be configured with the respective virtual addresses using the following PWRM configuration properties:

CM_BASEADDR
IVAMMU_BASEADDR
PRM_BASEADDR
SCM_BASEADDR

Base address of Clock Manager (CM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Clock Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: CM_BASEADDR
Type: Address
Example: bios.PWRM.CM_BASEADDR = 0x12004000

Base address of IVA MMU. When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the IVA MMU. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: IVAMMU_BASEADDR
Type: Address
Example: bios.PWRM.IVAMMU_BASEADDR = 0x12005000

Base address of Power & Reset Manager (PRM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Power & Reset Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: PRM_BASEADDR
Type: Address
Example: bios.PWRM.PRM_BASEADDR = 0x12006000

Base address of System Control Module (SCM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the System Control Module. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: SCM_BASEADDR
Type: Address
Example: bios.PWRM.SCM_BASEADDR = 0x12007000

    Davinci 1.x IDMA0 problem workaround -- A custom version of the HWI dispatcher was created to  work around an IDMA0/MMR problem in rev 1.x DM644x devices (see SPRZ241 - "TMS320DM6446 Digital Media System-on-chip Silicon Errata" for more information about this errata).  This errata is only present in Rev 1.x DM644x devices and is not present on other 64x+ devices.
 The HWI dispatcher has been updated to poll the IDMA0 status register and wait for IDMA0 transfer to complete before calling the actual ISR.  This will ensure that the ISR will not reference an MMR register while the IDMA0 is active.  This will also ensure that an asynchronous task switch will not occur while the IDMA0 is active.  This may affect interrupt response time, but should not be a problem in most applications since IDMA0 jobs are usually fairly short.  This workaround is only supported by the HWI dispatcher (the HWI_enter/exit macros do not contain the workaround).
 A hidden configuration parameter (bios.GBL.USEIDMA0DISPATCHER) is used to select this alternate version of the dispatcher.  This parameter has default value 'true' for DM644x and DM42x configurations.  This parameter has default value 'false' for all other 64x+ configurations.  The user can set this parameter to 'false' if they do not want this workaround used in their Davinci applications (e.g., if their application is not using IDMA0 and/or they know that that their ISRs do not reference MMR registers).

    Memory heap issue when updating  existing configuration files -- Prior versions of the configuration tool allowed for an inconsistent memory heap configuration.   The tool allowed users to enable heaps when no heaps were actually configured and the default for bios.MEM.MALLOCSEG and bios.MEM.SEGZERO were still set to 'MEM_NULL'.  This was causing problems in applications since malloc() and MEM_alloc() were failing even when user thought they had configured BIOS for dynamic memory allocation.  The configuration tool is now checking to make sure that configurations that have heaps also have bios.MEM.MALLOCSEG and bios.MEM.SEGZERO set to a valid heap.  Update from existing projects might yield an error message.  The work around is to either remove the 'bios.enableMemoryHeaps(prog);' line from your configuration, or to add a heap and set bios.MEM.MALLOCSEG and bios.MEM.SEGZERO accordingly.  See the ti/bios/examples/common/evmDM6446_common.tci file (or others) for an example of how to do this.

   Gconf uses wrong parameters when more than one pjt is opened and they share the same .tcf file -- When more than one CCS project (.pjt file) share the same .tcf file, and two or more of the projects are opened in CCS, opening a .tcf from one of the projects will launch GConf using the DspBiosBuilder builder parameters defined for the most recently opened project. This may result in incorrect base seed properties and import file paths in the .tcf file being edited. To workaround, do not share .tcf files between projects. This is tracked by SDSCM00003834

  BIOS RTA has problems reading data in stop mode for some 64x+ devices -- Currently, stop mode reads will only work for DaVinci. This is tracked by SDSCM00010400

    DSP/BIOS examples that are using RTA halt when run every other time on DSK5510/DSK5509A via XDS560. This is tracked by SDSCM00005820.

    CCS window closes on refreshing KOV Window when it receives illegal values -- KOV will crash if Module Objects have illegal values. For e.g if a dynamic task has a bad name, KOV will try to print the illegal name and crash. This is tracked by SDSCM00006694.   

    KOV window shows wrong names for dynamic objects -- This is tracked by SDSCM00007151.

    KOV displays wrong names for memory sections -- This is tracked by SDSCM00004917.

    Incorrect platform name in Tconf User's Guide in "Create New Platform" section -- The spru0007h.pdf document contains the correct instructions for creating a new platform using the Tconf's User's Guide, the help files were not updated to reflect the same naming convention. This is tracked by SDSCM00003471.

    RTDX tutorial examples do not all execute as expected  when run on TCI6482 simulator little endian -- This is tracked by SDSSCM00010736.

    RTDX Hot-Connect does not work for C64P -- This is tracked by SDSSCM00011954.

    RTA (VBD) crash after lots of disconnects and connects -- This is tracked by SDSSCM00012471.

Fixed In This Release

The following bugs and enhancements have been fixed in this release.  These are also listed in the sub-component release notes, but provided here for convenience.


id Headline
SDSCM00017352 DSP/BIOS DRA442 support uses wrong timer (RTI2)
SDSCM00017103 IMCOP memory should be removed from DM647/8 catalog files
SDSCM00016997 DIO static creation option causes corruption of OBJ table
SDSCM00016889 BIOS CLK default for DM647/8 should be CPU / 6 (currently is == CPU)
SDSCM00016888 fix the default frequency for evmDM648 board
SDSCM00016820 export gio_new.c to to product so customers have complete GIO source
SDSCM00016566 add bios_DM6441.tci file to fully support DM6441 (catalog added in 5.31.06)
SDSCM00016558 Stairstep project file missing source file entries for evm6424 in stairstep.pjt
SDSCM00012424 Need to check out DM647/8 EMIF ranges for BCACHE and interrupt events


Validation Information

Codegen versions used in BIOS 5.31.05 product validation. See kernel release notes for the compiler versions used to build the target content.

ISA

Compiler version(s)

c6x v6.0.8
c55x v3.3.2
c54x v4.1.0
c28x v4.1.3

 

Deprecation Notice

 

Deprecated DSP/BIOS APIs: Some DSP/BIOS APIs are being deprecated and will no longer be supported in the next major release of DSP/BIOS.

These APIs are still supported in DSP/BIOS 5.31.07 and will be supported in any patch releases or minor enhancements to DSP/BIOS 5.31.

 

The deprecated APIs are:

 

All APIs associated with the DEV driver interface. Developers are recommended to use the IOM driver interface.

 

DEV_createDevice

DEV_deleteDevice

DEV_match

Dxx_close

Dxx_ctrl

Dxx_idle

Dxx_init

Dxx_issue

Dxx_open

Dxx_ready

Dxx_reclaim

DGN Driver

DGS Driver

DHL Driver

 

All APIs associated with the PIP module. Developers are recommended to use the SIO module.

 

PIP_alloc

PIP_free

PIP_get

PIP_getReaderAddr

PIP_getReaderNumFrames

PIP_getReaderSize

PIP_getWriterAddr

PIP_getWriterNumFrames

PIP_getWriterSize

PIP_peek

PIP_put                                                                                        

PIP_reset

PIP_setWriterSize

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_31.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.31.00.01 with directory  bios_5_31_00_01) and the final release will be bios_5_31 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.31.03 with directory bios_5_31_03.  

Point releases where new features such as additional device support are released same as major baselines, i.e., with patch counter of zero and removed from directory qualifier, ex. 5.31 with directory bios_5_31.  When referring to the release, the term bios "five dot thirty-one" generally refers to the baseline bios 5.31 and the patches (ex. 5.31.03) and point releases (ex. 5.32) that comprise the compatible group.




DSP/BIOS v5.31.06 Release Notes

 

Last updated:  11 April 2007

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Known Issues", "Fixed In This Release", and "Validation Info".   

Check the following web site for updates: https://www-a.ti.com/downloads/sds_support/targetcontent/bios/index.html

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package
  DSP/BIOS Kernel Benchmarks
  XDC Tools (Tconf) Package (updated)
  DSP/BIOS Platforms (updated)
  DSP/BIOS Examples
  Real Time Data Exchange (RTDX)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support)
  DSP/BIOS Help Files
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD)
  DSP/BIOS Graphical Configuration Tool (Gconf)

General Information

DSP/BIOS 5.31.06 is an all ISA release and can be used with CCS 3.2, CCS 3.3 or later. This will be installed in <installdir>/bios_5_31_06.

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.31.06

Device Support

     
  Devices Supported* Runtime model
 

*BIOS Configuration DeviceName listed

 
     
28xx Devices    
  F2801
F2806
F2808
F2810
F2811
F2812
 
Large model
     
54xx Devices    
 
5402
5402A
5409A
5416
5470
5471
5405
 
Near and Far model supported
     
55xx Devices    
 

5501
5502
5503
5507
5509A
DA255
5510
5510A
5561

 

Large model on Laijin 2.x core devices

Note: 55xx small model support has been dropped starting with BIOS 5.10

 

5903 (OMAP)
5905
(OMAP)

5910 (OMAP)
5912 (OMAP)

5948 (OMAP)
5946 (OMAP)
5944 (OMAP)


1035 (OMAP)
1510 (OMAP)
1610 (OMAP)
1710 (OMAP)
2320 (OMAP)
2420 (OMAP)
 

TNETV1055

Large model for 55xx DSP side of Heterogeneous multi processors (OMAP: ARM + 55xx DSP, Titan: MIPS + 55xx DSP)

Large and Huge model for 55xx DSP on Laijin 2.x/3.x, such as OMAP1710, OMAP2420

Note: 55xx small model support has been dropped starting with BIOS 5.10

     
62xx Devices    
  Not Supported: C6201
6202
6203
6204
6205
6211

 

Big and Little Endian
     
67xx Devices    
6701
6711
6711 - 250
6712
6713
6713 - 300
 

 

Big and Little Endian
     
64xx Devices    
  6410
6411
6412
6413
6414
6415
6416
6418
DRI300
DM640
DM641
DM642
Big and Little Endian
     
64P  Devices    

DM420
DM415
DM425
DM426

DM647

DM648

 

DM6431
DM6433
DM6435

DM6437
DM6443
DM6446

 

6421
6424
6452
6455
6454

 

TCI6482

TCI6486
TCI6487
TCI6488

 

DRA442
DRA446

 


2430 (OMAP)
3430 (OMAP)

Big and Little Endian
     
67P  Devices    
  6727

DA705
DA707
DA710

Little Endian
     
IAG Devices    
  DM270
DM310
DM320

DM420
DA300
DA295

 

Known Issues

    Please check the following link for additional information when upgrading from 4.90 to 5.x -- Knowledge base with known 4.90 to 5.x upgrade issues

   OMAP2430/3430 HWI/WUGEN API Documentation -- The new HWI/WUGEN APIs are not documented in the BIOS API Guide.  This is tracked by SDSCM00016107 which contains documentation for each API.

    PWRM/3430 Documentation Update -- When the IVA MMU is enabled and PWRM is enabled, the base addresses of the support modules must be mapped into the IVA MMU and BIOS must be configured with the respective virtual addresses using the following PWRM configuration properties:

CM_BASEADDR
IVAMMU_BASEADDR
PRM_BASEADDR
SCM_BASEADDR

Base address of Clock Manager (CM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Clock Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: CM_BASEADDR
Type: Address
Example: bios.PWRM.CM_BASEADDR = 0x12004000

Base address of IVA MMU. When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the IVA MMU. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: IVAMMU_BASEADDR
Type: Address
Example: bios.PWRM.IVAMMU_BASEADDR = 0x12005000

Base address of Power & Reset Manager (PRM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Power & Reset Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: PRM_BASEADDR
Type: Address
Example: bios.PWRM.PRM_BASEADDR = 0x12006000

Base address of System Control Module (SCM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the System Control Module. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: SCM_BASEADDR
Type: Address
Example: bios.PWRM.SCM_BASEADDR = 0x12007000

    Davinci 1.x IDMA0 problem workaround -- A custom version of the HWI dispatcher was created to  work around an IDMA0/MMR problem in rev 1.x DM644x devices (see SPRZ241 - "TMS320DM6446 Digital Media System-on-chip Silicon Errata" for more information about this errata).  This errata is only present in Rev 1.x DM644x devices and is not present on other 64x+ devices.
 The HWI dispatcher has been updated to poll the IDMA0 status register and wait for IDMA0 transfer to complete before calling the actual ISR.  This will ensure that the ISR will not reference an MMR register while the IDMA0 is active.  This will also ensure that an asynchronous task switch will not occur while the IDMA0 is active.  This may affect interrupt response time, but should not be a problem in most applications since IDMA0 jobs are usually fairly short.  This workaround is only supported by the HWI dispatcher (the HWI_enter/exit macros do not contain the workaround).
 A hidden configuration parameter (bios.GBL.USEIDMA0DISPATCHER) is used to select this alternate version of the dispatcher.  This parameter has default value 'true' for DM644x and DM42x configurations.  This parameter has default value 'false' for all other 64x+ configurations.  The user can set this parameter to 'false' if they do not want this workaround used in their Davinci applications (e.g., if their application is not using IDMA0 and/or they know that that their ISRs do not reference MMR registers).

    Memory heap issue when updating  existing configuration files -- Prior versions of the configuration tool allowed for an inconsistent memory heap configuration.   The tool allowed users to enable heaps when no heaps were actually configured and the default for bios.MEM.MALLOCSEG and bios.MEM.SEGZERO were still set to 'MEM_NULL'.  This was causing problems in applications since malloc() and MEM_alloc() were failing even when user thought they had configured BIOS for dynamic memory allocation.  The configuration tool is now checking to make sure that configurations that have heaps also have bios.MEM.MALLOCSEG and bios.MEM.SEGZERO set to a valid heap.  Update from existing projects might yield an error message.  The work around is to either remove the 'bios.enableMemoryHeaps(prog);' line from your configuration, or to add a heap and set bios.MEM.MALLOCSEG and bios.MEM.SEGZERO accordingly.  See the ti/bios/examples/common/evmDM6446_common.tci file (or others) for an example of how to do this.

   Gconf uses wrong parameters when more than one pjt is opened and they share the same .tcf file -- When more than one CCS project (.pjt file) share the same .tcf file, and two or more of the projects are opened in CCS, opening a .tcf from one of the projects will launch GConf using the DspBiosBuilder builder parameters defined for the most recently opened project. This may result in incorrect base seed properties and import file paths in the .tcf file being edited. To workaround, do not share .tcf files between projects. This is tracked by SDSCM00003834

  BIOS RTA has problems reading data in stop mode for some 64x+ devices -- Currently, stop mode reads will only work for DaVinci. This is tracked by SDSCM00010400

    DSP/BIOS examples that are using RTA halt when run every other time on DSK5510/DSK5509A via XDS560. This is tracked by SDSCM00005820.

    CCS window closes on refreshing KOV Window when it receives illegal values -- KOV will crash if Module Objects have illegal values. For e.g if a dynamic task has a bad name, KOV will try to print the illegal name and crash. This is tracked by SDSCM00006694.   

    KOV window shows wrong names for dynamic objects -- This is tracked by SDSCM00007151.

    KOV displays wrong names for memory sections -- This is tracked by SDSCM00004917.

    Incorrect platform name in Tconf User's Guide in "Create New Platform" section -- The spru0007h.pdf document contains the correct instructions for creating a new platform using the Tconf's User's Guide, the help files were not updated to reflect the same naming convention. This is tracked by SDSCM00003471.

    RTDX tutorial examples do not all execute as expected  when run on TCI6482 simulator little endian -- This is tracked by SDSSCM00010736.

    RTDX Hot-Connect does not work for C64P -- This is tracked by SDSSCM00011954.

    RTA (VBD) crash after lots of disconnects and connects -- This is tracked by SDSSCM00012471.

    Stairstep project file missing source file entries for evm6424 in stairstep.pjt -- This is tracked by SDSSCM00016558.

Fixed In This Release

The following bugs and enhancements have been fixed in this release.  These are also listed in the sub-component release notes, but provided here for convenience.

id Headline
SDSCM00016374 DM6441 and DM6443 devices missing from ti.catalog.c6000 package
SDSCM00016297 ti.platforms.evmDM6446 and ti.platforms.evmDM6467 contain Arm9 device files
SDSCM00016294 evmDM6437 and evm6424 platform files have 2 sections named "DDR2"
SDSCM00016132 VICP/MEM base/length are incorrect in DM6446 catalog files

Validation Information

Codegen versions used in BIOS 5.31.05 product validation. See kernel release notes for the compiler versions used to build the target content.

ISA

Compiler version(s)

c6x v6.0.8
c55x v3.3.2
c54x v4.1.0
c28x v4.1.3

 

Deprecation Notice

 

Deprecated DSP/BIOS APIs: Some DSP/BIOS APIs are being deprecated and will no longer be supported in the next major release of DSP/BIOS.

These APIs are still supported in DSP/BIOS 5.31.06 and will be supported in any patch releases or minor enhancements to DSP/BIOS 5.31.

 

The deprecated APIs are:

 

All APIs associated with the DEV driver interface. Developers are recommended to use the IOM driver interface.

 

DEV_createDevice

DEV_deleteDevice

DEV_match

Dxx_close

Dxx_ctrl

Dxx_idle

Dxx_init

Dxx_issue

Dxx_open

Dxx_ready

Dxx_reclaim

DGN Driver

DGS Driver

DHL Driver

 

All APIs associated with the PIP module. Developers are recommended to use the SIO module.

 

PIP_alloc

PIP_free

PIP_get

PIP_getReaderAddr

PIP_getReaderNumFrames

PIP_getReaderSize

PIP_getWriterAddr

PIP_getWriterNumFrames

PIP_getWriterSize

PIP_peek

PIP_put                                                                                        

PIP_reset

PIP_setWriterSize

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_31.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.31.00.01 with directory  bios_5_31_00_01) and the final release will be bios_5_31 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.31.03 with directory bios_5_31_03.  

Point releases where new features such as additional device support are released same as major baselines, i.e., with patch counter of zero and removed from directory qualifier, ex. 5.31 with directory bios_5_31.  When referring to the release, the term bios "five dot thirty-one" generally refers to the baseline bios 5.31 and the patches (ex. 5.31.03) and point releases (ex. 5.32) that comprise the compatible group.



DSP/BIOS v5.31.05 Release Notes

 

Last updated:  28 Mar 2007

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Known Issues", "Fixed In This Release", and "Validation Info".   

Check the following web site for updates: https://www-a.ti.com/downloads/sds_support/targetcontent/bios/index.html

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package (updated)
  DSP/BIOS Kernel Benchmarks
  XDC Tools (Tconf) Package (updated)
  DSP/BIOS Platforms (updated)
  DSP/BIOS Examples (updated)
  Real Time Data Exchange (RTDX)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support)
  DSP/BIOS Help Files
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD)
  DSP/BIOS Graphical Configuration Tool (Gconf)

General Information

DSP/BIOS 5.31.05 is an All ISA release and can be used with CCS 3.2, CCS 3.3 or later. This will be installed in <installdir>/bios_5_31_05.

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.31.05

Device Support

     
  Devices Supported* Runtime model
 

*BIOS Configuration DeviceName listed

 
     
28xx Devices    
  F2801
F2806
F2808
F2810
F2811
F2812
 
Large model
     
54xx Devices    
 
5402
5402A
5409A
5416
5470
5471
5405
 
Near and Far model supported
     
55xx Devices    
 

5501
5502
5503
5507
5509A
DA255
5510
5510A
5561

 

Large model on Laijin 2.x core devices

Note: 55xx small model support has been dropped starting with BIOS 5.10

 

5903 (OMAP)
5905
(OMAP)

5910 (OMAP)
5912 (OMAP)

5948 (OMAP)
5946 (OMAP)
5944 (OMAP)


1035 (OMAP)
1510 (OMAP)
1610 (OMAP)
1710 (OMAP)
2320 (OMAP)
2420 (OMAP)
 

TNETV1055

Large model for 55xx DSP side of Heterogeneous multi processors (OMAP: ARM + 55xx DSP, Titan: MIPS + 55xx DSP)

Large and Huge model for 55xx DSP on Laijin 2.x/3.x, such as OMAP1710, OMAP2420

Note: 55xx small model support has been dropped starting with BIOS 5.10

     
62xx Devices    
  Not Supported: C6201
6202
6203
6204
6205
6211

 

Big and Little Endian
     
67xx Devices    
6701
6711
6711 - 250
6712
6713
6713 - 300
 

 

Big and Little Endian
     
64xx Devices    
  6410
6411
6412
6413
6414
6415
6416
6418
DRI300
DM640
DM641
DM642
Big and Little Endian
     
64P  Devices    

DM420
DM415
DM425
DM426

DM647

DM648

 

DM6431
DM6433
DM6435

DM6437
DM6443
DM6446

 

6421
6424
6452
6455
6454

 

TCI6482

TCI6486
TCI6487
TCI6488

 

DRA442
DRA446

 


2430 (OMAP)
3430 (OMAP)

Big and Little Endian
     
67P  Devices    
  6727

DA705
DA707
DA710

Little Endian
     
IAG Devices    
  DM270
DM310
DM320

DM420
DA300
DA295

 

Known Issues

    Please check the following link for additional information when upgrading from 4.90 to 5.x -- Knowledge base with known 4.90 to 5.x upgrade issues

   OMAP2430/3430 HWI/WUGEN API Documentation -- The new HWI/WUGEN APIs are not documented in the BIOS API Guide.  This is tracked by SDSCM00016107 which contains documentation for each API.

    PWRM/3430 Documentation Update -- When the IVA MMU is enabled and PWRM is enabled, the base addresses of the support modules must be mapped into the IVA MMU and BIOS must be configured with the respective virtual addresses using the following PWRM configuration properties:

CM_BASEADDR
IVAMMU_BASEADDR
PRM_BASEADDR
SCM_BASEADDR

Base address of Clock Manager (CM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Clock Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: CM_BASEADDR
Type: Address
Example: bios.PWRM.CM_BASEADDR = 0x12004000

Base address of IVA MMU. When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the IVA MMU. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: IVAMMU_BASEADDR
Type: Address
Example: bios.PWRM.IVAMMU_BASEADDR = 0x12005000

Base address of Power & Reset Manager (PRM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Power & Reset Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: PRM_BASEADDR
Type: Address
Example: bios.PWRM.PRM_BASEADDR = 0x12006000

Base address of System Control Module (SCM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the System Control Module. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: SCM_BASEADDR
Type: Address
Example: bios.PWRM.SCM_BASEADDR = 0x12007000

    Davinci 1.x IDMA0 problem workaround -- A custom version of the HWI dispatcher was created to  work around an IDMA0/MMR problem in rev 1.x DM644x devices (see SPRZ241 - "TMS320DM6446 Digital Media System-on-chip Silicon Errata" for more information about this errata).  This errata is only present in Rev 1.x DM644x devices and is not present on other 64x+ devices.
 The HWI dispatcher has been updated to poll the IDMA0 status register and wait for IDMA0 transfer to complete before calling the actual ISR.  This will ensure that the ISR will not reference an MMR register while the IDMA0 is active.  This will also ensure that an asynchronous task switch will not occur while the IDMA0 is active.  This may affect interrupt response time, but should not be a problem in most applications since IDMA0 jobs are usually fairly short.  This workaround is only supported by the HWI dispatcher (the HWI_enter/exit macros do not contain the workaround).
 A hidden configuration parameter (bios.GBL.USEIDMA0DISPATCHER) is used to select this alternate version of the dispatcher.  This parameter has default value 'true' for DM644x and DM42x configurations.  This parameter has default value 'false' for all other 64x+ configurations.  The user can set this parameter to 'false' if they do not want this workaround used in their Davinci applications (e.g., if their application is not using IDMA0 and/or they know that that their ISRs do not reference MMR registers).

    Memory heap issue when updating  existing configuration files -- Prior versions of the configuration tool allowed for an inconsistent memory heap configuration.   The tool allowed users to enable heaps when no heaps were actually configured and the default for bios.MEM.MALLOCSEG and bios.MEM.SEGZERO were still set to 'MEM_NULL'.  This was causing problems in applications since malloc() and MEM_alloc() were failing even when user thought they had configured BIOS for dynamic memory allocation.  The configuration tool is now checking to make sure that configurations that have heaps also have bios.MEM.MALLOCSEG and bios.MEM.SEGZERO set to a valid heap.  Update from existing projects might yield an error message.  The work around is to either remove the 'bios.enableMemoryHeaps(prog);' line from your configuration, or to add a heap and set bios.MEM.MALLOCSEG and bios.MEM.SEGZERO accordingly.  See the ti/bios/examples/common/evmDM6446_common.tci file (or others) for an example of how to do this.

   Gconf uses wrong parameters when more than one pjt is opened and they share the same .tcf file -- When more than one CCS project (.pjt file) share the same .tcf file, and two or more of the projects are opened in CCS, opening a .tcf from one of the projects will launch GConf using the DspBiosBuilder builder parameters defined for the most recently opened project. This may result in incorrect base seed properties and import file paths in the .tcf file being edited. To workaround, do not share .tcf files between projects. This is tracked by SDSCM00003834

  BIOS RTA has problems reading data in stop mode for some 64x+ devices -- Currently, stop mode reads will only work for DaVinci. This is tracked by SDSCM00010400

    DSP/BIOS examples that are using RTA halt when run every other time on DSK5510/DSK5509A via XDS560. This is tracked by SDSCM00005820.

    CCS window closes on refreshing KOV Window when it receives illegal values -- KOV will crash if Module Objects have illegal values. For e.g if a dynamic task has a bad name, KOV will try to print the illegal name and crash. This is tracked by SDSCM00006694.   

    KOV window shows wrong names for dynamic objects -- This is tracked by SDSCM00007151.

    KOV displays wrong names for memory sections -- This is tracked by SDSCM00004917.

    Incorrect platform name in Tconf User's Guide in "Create New Platform" section -- The spru0007h.pdf document contains the correct instructions for creating a new platform using the Tconf's User's Guide, the help files were not updated to reflect the same naming convention. This is tracked by SDSCM00003471.

    RTDX tutorial examples do not all execute as expected  when run on TCI6482 simulator little endian -- This is tracked by SDSSCM00010736.

    RTDX Hot-Connect does not work for C64P -- This is tracked by SDSSCM00011954.

    RTA (VBD) crash after lots of disconnects and connects -- This is tracked by SDSSCM00012471.

Fixed In This Release

The following bugs and enhancements have been fixed in this release.  These are also listed in the sub-component release notes, but provided here for convenience.

id Headline
SDSCM00015917 OMAP2320 mnemonic form of HWI_enter macro is broken
SDSCM00015807 DM6437 should have CLK.RESETTIMER=true by default
SDSCM00015609 TSK_create() should pad stack size to multiple of stack alignment
SDSCM00015581 Create BIOS examples for evm6424
SDSCM00015406 need platform file for evm6424
SDSCM00015280 DSP/BIOS must support OMAP1035
SDSCM00014962 Incorrect unmasking of interrupt in WUGEN causes IVA2 to be in bad power state
SDSCM00014760 request GIO_new() API sio GIO can be used w/o internal MEM_alloc calls
SDSCM00014184 makefile,64P in the examples folder has an error

Validation Information

Codegen versions used in BIOS 5.31.05 product validation. See kernel release notes for the compiler versions used to build the target content.

ISA

Compiler version(s)

c6x v6.0.8
c55x v3.3.2
c54x v4.1.0
c28x v4.1.3

 

Deprecation Notice

 

Deprecated DSP/BIOS APIs: Some DSP/BIOS APIs are being deprecated and will no longer be supported in the next major release of DSP/BIOS.

These APIs are still supported in DSP/BIOS 5.31.03 and will be supported in any patch releases or minor enhancements to DSP/BIOS 5.31.

 

The deprecated APIs are:

 

All APIs associated with the DEV driver interface. Developers are recommended to use the IOM driver interface.

 

DEV_createDevice

DEV_deleteDevice

DEV_match

Dxx_close

Dxx_ctrl

Dxx_idle

Dxx_init

Dxx_issue

Dxx_open

Dxx_ready

Dxx_reclaim

DGN Driver

DGS Driver

DHL Driver

 

All APIs associated with the PIP module. Developers are recommended to use the SIO module.

 

PIP_alloc

PIP_free

PIP_get

PIP_getReaderAddr

PIP_getReaderNumFrames

PIP_getReaderSize

PIP_getWriterAddr

PIP_getWriterNumFrames

PIP_getWriterSize

PIP_peek

PIP_put                                                                                        

PIP_reset

PIP_setWriterSize

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_31.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.31.00.01 with directory  bios_5_31_00_01) and the final release will be bios_5_31 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.31.03 with directory bios_5_31_03.  

Point releases where new features such as additional device support are released same as major baselines, i.e., with patch counter of zero and removed from directory qualifier, ex. 5.31 with directory bios_5_31.  When referring to the release, the term bios "five dot thirty-one" generally refers to the baseline bios 5.31 and the patches (ex. 5.31.03) and point releases (ex. 5.32) that comprise the compatible group.



DSP/BIOS v5.31.04 Release Notes

 

Last updated:  08 Feb 2007

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Known Issues", "Fixed In This Release", and "Validation Info".   

Check the following web site for updates: https://www-a.ti.com/downloads/sds_support/targetcontent/bios/index.html

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package (updated)
  DSP/BIOS Kernel Benchmarks
  XDC Tools (Tconf) Package
  DSP/BIOS Platforms
  DSP/BIOS Examples
  Real Time Data Exchange (RTDX)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support)
  DSP/BIOS Help Files
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD)
  DSP/BIOS Graphical Configuration Tool (Gconf)

General Information

DSP/BIOS 5.31.04 is an All ISA release and can be used with CCS 3.2, CCS 3.3 or later. This will be installed in <installdir>/bios_5_31_04.

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.31.04

Device Support

     
  Devices Supported* Runtime model
 

*BIOS Configuration DeviceName listed

 
     
28xx Devices    
  F2801
F2806
F2808
F2810
F2811
F2812
 
Large model
     
54xx Devices    
 
5402
5402A
5409A
5416
5470
5471
5405
 
Near and Far model supported
     
55xx Devices    
 

5501
5502
5503
5507
5509A
DA255
5510
5510A
5561

 

Large model on Laijin 2.x core devices

Note: 55xx small model support has been dropped starting with BIOS 5.10

 

5903 (OMAP)
5905
(OMAP)

5910 (OMAP)
5912 (OMAP)

5948 (OMAP)
5946 (OMAP)
5944 (OMAP)


1510 (OMAP)
1610 (OMAP)
1710 (OMAP)
2320 (OMAP)
2420 (OMAP)
 

TNETV1055

Large model for 55xx DSP side of Heterogeneous multi processors (OMAP: ARM + 55xx DSP, Titan: MIPS + 55xx DSP)

Large and Huge model for 55xx DSP on Laijin 2.x/3.x, such as OMAP1710, OMAP2420

Note: 55xx small model support has been dropped starting with BIOS 5.10

     
62xx Devices    
  Not Supported: C6201
6202
6203
6204
6205
6211

 

Big and Little Endian
     
67xx Devices    
6701
6711
6711 - 250
6712
6713
6713 - 300
 

 

Big and Little Endian
     
64xx Devices    
  6410
6411
6412
6413
6414
6415
6416
6418
DRI300
DM640
DM641
DM642
Big and Little Endian
     
64P  Devices    

DM420
DM415
DM425
DM426

DM647

DM648

 

DM6431
DM6433
DM6435

DM6437
DM6443
DM6446

 

6421
6424
6452
6455
6454

 

TCI6482

TCI6486
TCI6487
TCI6488

 

DRA442
DRA446

 


2430 (OMAP)
3430 (OMAP)

Big and Little Endian
     
67P  Devices    
  6727

DA705
DA707
DA710

Little Endian
     
IAG Devices    
  DM270
DM310
DM320

DM420
DA300
DA295

 

Known Issues

    Please check the following link for additional information when upgrading from 4.90 to 5.x -- Knowledge base with known 4.90 to 5.x upgrade issues

   PWRM/3430 Documentation Error --There is a typo in the DSP/BIOS Power Management AppNote document (SPRAA98). Its in a code example on how to set the wakeup event. The index values for sleepArgs should start at 0, not at 1. This is tracked by SDSCM00014100.

Incorrect version (page 28):

sleepArgs[1] = 0xFFFFFFBF; /* enable GP timer 5 as wakeup */
sleepArgs[2] = 0x0000FFFF; /* no wakeups via WUGEN_MEVT1 */
sleepArgs[3] = 0x000FFFFF; /* no wakeups via WUGEN_MEVT2 */
sleepArgs[4] = 0x00000001; /* no wakeups via WUGEN_MEVT3 */

Correct version:

sleepArgs[0] = 0xFFFFFFBF; /* enable GP timer 5 as wakeup */
sleepArgs[1] = 0x0000FFFF; /* no wakeups via WUGEN_MEVT1 */
sleepArgs[2] = 0x000FFFFF; /* no wakeups via WUGEN_MEVT2 */
sleepArgs[3] = 0x00000001; /* no wakeups via WUGEN_MEVT3 */

    PWRM/3430 Documentation Update -- When the IVA MMU is enabled and PWRM is enabled, the base addresses of the support modules must be mapped into the IVA MMU and BIOS must be configured with the respective virtual addresses using the following PWRM configuration properties:

CM_BASEADDR
IVAMMU_BASEADDR
PRM_BASEADDR
SCM_BASEADDR

Base address of Clock Manager (CM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Clock Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: CM_BASEADDR
Type: Address
Example: bios.PWRM.CM_BASEADDR = 0x12004000

Base address of IVA MMU. When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the IVA MMU. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: IVAMMU_BASEADDR
Type: Address
Example: bios.PWRM.IVAMMU_BASEADDR = 0x12005000

Base address of Power & Reset Manager (PRM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Power & Reset Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: PRM_BASEADDR
Type: Address
Example: bios.PWRM.PRM_BASEADDR = 0x12006000

Base address of System Control Module (SCM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the System Control Module. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: SCM_BASEADDR
Type: Address
Example: bios.PWRM.SCM_BASEADDR = 0x12007000

    Examples "makefile,64P" issue -- The provided makefile,64P in the examples directory for building all 64P devices has an error in it. There is a ")" where there should be a "\". This can be corrected or the user can build the individual examples using the provided makefiles for each. This is tracked by SDSCM00014184.

    Davinci 1.x IDMA0 problem workaround -- A custom version of the HWI dispatcher was created to  work around an IDMA0/MMR problem in rev 1.x DM644x devices (see SPRZ241 - "TMS320DM6446 Digital Media System-on-chip Silicon Errata" for more information about this errata).  This errata is only present in Rev 1.x DM644x devices and is not present on other 64x+ devices.
 The HWI dispatcher has been updated to poll the IDMA0 status register and wait for IDMA0 transfer to complete before calling the actual ISR.  This will ensure that the ISR will not reference an MMR register while the IDMA0 is active.  This will also ensure that an asynchronous task switch will not occur while the IDMA0 is active.  This may affect interrupt response time, but should not be a problem in most applications since IDMA0 jobs are usually fairly short.  This workaround is only supported by the HWI dispatcher (the HWI_enter/exit macros do not contain the workaround).
 A hidden configuration parameter (bios.GBL.USEIDMA0DISPATCHER) is used to select this alternate version of the dispatcher.  This parameter has default value 'true' for DM644x and DM42x configurations.  This parameter has default value 'false' for all other 64x+ configurations.  The user can set this parameter to 'false' if they do not want this workaround used in their Davinci applications (e.g., if their application is not using IDMA0 and/or they know that that their ISRs do not reference MMR registers).

    Memory heap issue when updating  existing configuration files -- Prior versions of the configuration tool allowed for an inconsistent memory heap configuration.   The tool allowed users to enable heaps when no heaps were actually configured and the default for bios.MEM.MALLOCSEG and bios.MEM.SEGZERO were still set to 'MEM_NULL'.  This was causing problems in applications since malloc() and MEM_alloc() were failing even when user thought they had configured BIOS for dynamic memory allocation.  The configuration tool is now checking to make sure that configurations that have heaps also have bios.MEM.MALLOCSEG and bios.MEM.SEGZERO set to a valid heap.  Update from existing projects might yield an error message.  The work around is to either remove the 'bios.enableMemoryHeaps(prog);' line from your configuration, or to add a heap and set bios.MEM.MALLOCSEG and bios.MEM.SEGZERO accordingly.  See the ti/bios/examples/common/evmDM6446_common.tci file (or others) for an example of how to do this.

   Gconf uses wrong parameters when more than one pjt is opened and they share the same .tcf file -- When more than one CCS project (.pjt file) share the same .tcf file, and two or more of the projects are opened in CCS, opening a .tcf from one of the projects will launch GConf using the DspBiosBuilder builder parameters defined for the most recently opened project. This may result in incorrect base seed properties and import file paths in the .tcf file being edited. To workaround, do not share .tcf files between projects. This is tracked by SDSCM00003834

  BIOS RTA has problems reading data in stop mode for some 64x+ devices -- Currently, stop mode reads will only work for DaVinci. This is tracked by SDSCM00010400

    DSP/BIOS examples that are using RTA halt when run every other time on DSK5510/DSK5509A via XDS560. This is tracked by SDSCM00005820.

    CCS window closes on refreshing KOV Window when it receives illegal values -- KOV will crash if Module Objects have illegal values. For e.g if a dynamic task has a bad name, KOV will try to print the illegal name and crash. This is tracked by SDSCM00006694.   

    KOV window shows wrong names for dynamic objects -- This is tracked by SDSCM00007151.

    KOV displays wrong names for memory sections -- This is tracked by SDSCM00004917.

    Incorrect platform name in Tconf User's Guide in "Create New Platform" section -- The spru0007h.pdf document contains the correct instructions for creating a new platform using the Tconf's User's Guide, the help files were not updated to reflect the same naming convention. This is tracked by SDSCM00003471.

    RTDX tutorial examples do not all execute as expected  when run on TCI6482 simulator little endian -- This is tracked by SDSSCM00010736.

    RTDX Hot-Connect does not work for C64P -- This is tracked by SDSSCM00011954.

    RTA (VBD) crash after lots of disconnects and connects -- This is tracked by SDSSCM00012471.

Fixed In This Release

The following bugs and enhancements have been fixed in this release.  These are also listed in the sub-component release notes, but provided here for convenience.

id Headline
SDSCM00015030 timestamp LOG for 62x/64x/67x should store 64-bit timestamp 
SDSCM00014627 PWRM module using GPTimer physical address for resource ID assignment.
SDSCM00014550  some include/*.h64P files have incorrect permission bit settings
SDSCM00014452  Timestamped LOGs for C64+ corrupt stack
SDSCM00013827 BIOS does not allow HS-RTDX for 671x 

Validation Information

Codegen versions used in BIOS 5.31.03 product validation. See kernel release notes for the compiler versions used to build the target content.

ISA

Compiler version(s)

c6x v6.0.8
c55x v3.3.2
c54x v4.1.0
c28x v4.1.3

 

Deprecation Notice

 

Deprecated DSP/BIOS APIs: Some DSP/BIOS APIs are being deprecated and will no longer be supported in the next major release of DSP/BIOS.

These APIs are still supported in DSP/BIOS 5.31.03 and will be supported in any patch releases or minor enhancements to DSP/BIOS 5.31.

 

The deprecated APIs are:

 

All APIs associated with the DEV driver interface. Developers are recommended to use the IOM driver interface.

 

DEV_createDevice

DEV_deleteDevice

DEV_match

Dxx_close

Dxx_ctrl

Dxx_idle

Dxx_init

Dxx_issue

Dxx_open

Dxx_ready

Dxx_reclaim

DGN Driver

DGS Driver

DHL Driver

 

All APIs associated with the PIP module. Developers are recommended to use the SIO module.

 

PIP_alloc

PIP_free

PIP_get

PIP_getReaderAddr

PIP_getReaderNumFrames

PIP_getReaderSize

PIP_getWriterAddr

PIP_getWriterNumFrames

PIP_getWriterSize

PIP_peek

PIP_put                                                                                        

PIP_reset

PIP_setWriterSize

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_31.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.31.00.01 with directory  bios_5_31_00_01) and the final release will be bios_5_31 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.31.03 with directory bios_5_31_03.  

Point releases where new features such as additional device support are released same as major baselines, i.e., with patch counter of zero and removed from directory qualifier, ex. 5.31 with directory bios_5_31.  When referring to the release, the term bios "five dot thirty-one" generally refers to the baseline bios 5.31 and the patches (ex. 5.31.03) and point releases (ex. 5.32) that comprise the compatible group.



 

DSP/BIOS v5.31.03 Release Notes

 

Last updated:  21 Dec 2006

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Known Issues", "Fixed In This Release", and "Validation Info".   

Check the following web site for updates: https://www-a.ti.com/downloads/sds_support/targetcontent/bios/index.html

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package (updated)
  DSP/BIOS Kernel Benchmarks
  XDC Tools (Tconf) Package (updated)
  DSP/BIOS Platforms (updated)
  DSP/BIOS Examples
  Real Time Data Exchange (RTDX)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support)
  DSP/BIOS Help Files
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD) (updated)
  DSP/BIOS Graphical Configuration Tool (Gconf)

General Information

DSP/BIOS 5.31.03 is an All ISA release and can be used with CCS 3.2, CCS 3.3 or later. This will be installed in <installdir>/bios_5_31_03.

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.31.03

Device Support

     
  Devices Supported* Runtime model
 

*BIOS Configuration DeviceName listed

 
     
28xx Devices    
  F2801
F2806
F2808
F2810
F2811
F2812
 
Large model
     
54xx Devices    
 
5402
5402A
5409A
5416
5470
5471
5405
 
Near and Far model supported
     
55xx Devices    
 

5501
5502
5503
5507
5509A
DA255
5510
5510A
5561

 

Large model on Laijin 2.x core devices

Note: 55xx small model support has been dropped starting with BIOS 5.10

 

5903 (OMAP)
5905
(OMAP)

5910 (OMAP)
5912 (OMAP)

5948 (OMAP)
5946 (OMAP)
5944 (OMAP)


1510 (OMAP)
1610 (OMAP)
1710 (OMAP)
2320 (OMAP)
2420 (OMAP)
 

TNETV1055

Large model for 55xx DSP side of Heterogeneous multi processors (OMAP: ARM + 55xx DSP, Titan: MIPS + 55xx DSP)

Large and Huge model for 55xx DSP on Laijin 2.x/3.x, such as OMAP1710, OMAP2420

Note: 55xx small model support has been dropped starting with BIOS 5.10

     
62xx Devices    
  Not Supported: C6201
6202
6203
6204
6205
6211

 

Big and Little Endian
     
67xx Devices    
6701
6711
6711 - 250
6712
6713
6713 - 300
 

 

Big and Little Endian
     
64xx Devices    
  6410
6411
6412
6413
6414
6415
6416
6418
DRI300
DM640
DM641
DM642
Big and Little Endian
     
64P  Devices    

DM420
DM415
DM425
DM426

DM647

DM648

 

DM6431
DM6433
DM6435

DM6437
DM6443
DM6446

 

6421
6424
6452
6455
6454

 

TCI6482

TCI6486
TCI6487
TCI6488

 

DRA442
DRA446

 


2430 (OMAP)
3430 (OMAP)

Big and Little Endian
     
67P  Devices    
  6727

DA705
DA707
DA710

Little Endian
     
IAG Devices    
  DM270
DM310
DM320

DM420
DA300
DA295

 

Known Issues

    Please check the following link for additional information when upgrading from 4.90 to 5.x -- Knowledge base with known 4.90 to 5.x upgrade issues

   PWRM/3430 Documentation Error --There is a typo in the DSP/BIOS Power Management AppNote document (SPRAA98). Its in a code example on how to set the wakeup event. The index values for sleepArgs should start at 0, not at 1. This is tracked by SDSCM00014100.

Incorrect version (page 28):

sleepArgs[1] = 0xFFFFFFBF; /* enable GP timer 5 as wakeup */
sleepArgs[2] = 0x0000FFFF; /* no wakeups via WUGEN_MEVT1 */
sleepArgs[3] = 0x000FFFFF; /* no wakeups via WUGEN_MEVT2 */
sleepArgs[4] = 0x00000001; /* no wakeups via WUGEN_MEVT3 */

Correct version:

sleepArgs[0] = 0xFFFFFFBF; /* enable GP timer 5 as wakeup */
sleepArgs[1] = 0x0000FFFF; /* no wakeups via WUGEN_MEVT1 */
sleepArgs[2] = 0x000FFFFF; /* no wakeups via WUGEN_MEVT2 */
sleepArgs[3] = 0x00000001; /* no wakeups via WUGEN_MEVT3 */

    PWRM/3430 Documentation Update -- When the IVA MMU is enabled and PWRM is enabled, the base addresses of the support modules must be mapped into the IVA MMU and BIOS must be configured with the respective virtual addresses using the following PWRM configuration properties:

CM_BASEADDR
IVAMMU_BASEADDR
PRM_BASEADDR
SCM_BASEADDR

Base address of Clock Manager (CM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Clock Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: CM_BASEADDR
Type: Address
Example: bios.PWRM.CM_BASEADDR = 0x12004000

Base address of IVA MMU. When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the IVA MMU. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: IVAMMU_BASEADDR
Type: Address
Example: bios.PWRM.IVAMMU_BASEADDR = 0x12005000

Base address of Power & Reset Manager (PRM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the Power & Reset Manager. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: PRM_BASEADDR
Type: Address
Example: bios.PWRM.PRM_BASEADDR = 0x12006000

Base address of System Control Module (SCM). When enabling the IVA MMU, use this configuration property to specify the virtual address mapped to the physical address of the System Control Module. The IVA MMU must map one page (4K bytes) of virtual memory starting at the given address.

Tconf Name: SCM_BASEADDR
Type: Address
Example: bios.PWRM.SCM_BASEADDR = 0x12007000

    Examples "makefile,64P" issue -- The provided makefile,64P in the examples directory for building all 64P devices has an error in it. There is a ")" where there should be a "\". This can be corrected or the user can build the individual examples using the provided makefiles for each. This is tracked by SDSCM00014184.

    Davinci 1.x IDMA0 problem workaround -- A custom version of the HWI dispatcher was created to  work around an IDMA0/MMR problem in rev 1.x DM644x devices (see SPRZ241 - "TMS320DM6446 Digital Media System-on-chip Silicon Errata" for more information about this errata).  This errata is only present in Rev 1.x DM644x devices and is not present on other 64x+ devices.
 The HWI dispatcher has been updated to poll the IDMA0 status register and wait for IDMA0 transfer to complete before calling the actual ISR.  This will ensure that the ISR will not reference an MMR register while the IDMA0 is active.  This will also ensure that an asynchronous task switch will not occur while the IDMA0 is active.  This may affect interrupt response time, but should not be a problem in most applications since IDMA0 jobs are usually fairly short.  This workaround is only supported by the HWI dispatcher (the HWI_enter/exit macros do not contain the workaround).
 A hidden configuration parameter (bios.GBL.USEIDMA0DISPATCHER) is used to select this alternate version of the dispatcher.  This parameter has default value 'true' for DM644x and DM42x configurations.  This parameter has default value 'false' for all other 64x+ configurations.  The user can set this parameter to 'false' if they do not want this workaround used in their Davinci applications (e.g., if their application is not using IDMA0 and/or they know that that their ISRs do not reference MMR registers).

    Memory heap issue when updating  existing configuration files -- Prior versions of the configuration tool allowed for an inconsistent memory heap configuration.   The tool allowed users to enable heaps when no heaps were actually configured and the default for bios.MEM.MALLOCSEG and bios.MEM.SEGZERO were still set to 'MEM_NULL'.  This was causing problems in applications since malloc() and MEM_alloc() were failing even when user thought they had configured BIOS for dynamic memory allocation.  The configuration tool is now checking to make sure that configurations that have heaps also have bios.MEM.MALLOCSEG and bios.MEM.SEGZERO set to a valid heap.  Update from existing projects might yield an error message.  The work around is to either remove the 'bios.enableMemoryHeaps(prog);' line from your configuration, or to add a heap and set bios.MEM.MALLOCSEG and bios.MEM.SEGZERO accordingly.  See the ti/bios/examples/common/evmDM6446_common.tci file (or others) for an example of how to do this.

   Gconf uses wrong parameters when more than one pjt is opened and they share the same .tcf file -- When more than one CCS project (.pjt file) share the same .tcf file, and two or more of the projects are opened in CCS, opening a .tcf from one of the projects will launch GConf using the DspBiosBuilder builder parameters defined for the most recently opened project. This may result in incorrect base seed properties and import file paths in the .tcf file being edited. To workaround, do not share .tcf files between projects. This is tracked by SDSCM00003834

  BIOS RTA has problems reading data in stop mode for some 64x+ devices -- Currently, stop mode reads will only work for DaVinci. This is tracked by SDSCM00010400

    DSP/BIOS examples that are using RTA halt when run every other time on DSK5510/DSK5509A via XDS560. This is tracked by SDSCM00005820.

    CCS window closes on refreshing KOV Window when it receives illegal values -- KOV will crash if Module Objects have illegal values. For e.g if a dynamic task has a bad name, KOV will try to print the illegal name and crash. This is tracked by SDSCM00006694.   

    KOV window shows wrong names for dynamic objects -- This is tracked by SDSCM00007151.

    KOV displays wrong names for memory sections -- This is tracked by SDSCM00004917.

    Incorrect platform name in Tconf User's Guide in "Create New Platform" section -- The spru0007h.pdf document contains the correct instructions for creating a new platform using the Tconf's User's Guide, the help files were not updated to reflect the same naming convention. This is tracked by SDSCM00003471.

    RTDX tutorial examples do not all execute as expected  when run on TCI6482 simulator little endian -- This is tracked by SDSSCM00010736.

    RTDX Hot-Connect does not work for C64P -- This is tracked by SDSSCM00011954.

    RTA (VBD) crash after lots of disconnects and connects -- This is tracked by SDSSCM00012471.

Fixed In This Release

The following bugs and enhancements have been fixed in this release.  These are also listed in the sub-component release notes, but provided here for convenience.

id Headline
SDSCM00014070 use 6.0.8 codegen to build BIOS libraries for all 6x
SDSCM00014018 Base addresses of CM, PRM, DSP MMU, and Control Module need to be configurable to support virtual addresses (3430/PWRM)
SDSCM00013991 Hibernation sleep mode is not restoring TSC enable state (3430/PWRM)
SDSCM00013990 DSP/BIOS release note navigation is partially broken
SDSCM00013931 Link error when using timer1on C62x
SDSCM00013905 Need a platform file for evmDRA446
SDSCM00013897 BIOS 5.31.01 evmDRA446 timer config code needs to be corrected
SDSCM00013881 Need to replace usage of ATSR.IDLE status bit with software-managed flag (3430/PWRM)
SDSCM00013849 Potential stack alignment issues when using HWI_enter/exit macros on the c6x
SDSCM00013792 New BIOS configuration will not save without enabling memory for heaps
SDSCM00013785 LOG_event for timestamp LOGS (LOG.TS=1) does not preserve B30:B31 when called from CLK_F_isr
SDSCM00013658 Provide BIOS platform file for TCI6488
SDSCM00013629 lowercase/uppercase problem with 5510 TCF file generated by cdb2tcf
SDSCM00013384 2320 CLK interrupt does not preserve AR0 register
SDSCM00012584 Possible corruption to B0 register in case of "fallThrough" of IDLE for 3430 hibernate (3430/PWRM)
SDSCM00012538 Default omap3430 configuration will cause linker errors
SDSCM00010342 BIOS does not create a reset vector at address 0x800000 for TCI6482 or 6455

Validation Information

Codegen versions used in BIOS 5.31.03 product validation. See kernel release notes for the compiler versions used to build the target content.

ISA

Compiler version(s)

c6x v6.0.8
c55x v3.3.2
c54x v4.1.0
c28x v4.1.3

 

Deprecation Notice

 

Deprecated DSP/BIOS APIs: Some DSP/BIOS APIs are being deprecated and will no longer be supported in the next major release of DSP/BIOS.

These APIs are still supported in DSP/BIOS 5.31.03 and will be supported in any patch releases or minor enhancements to DSP/BIOS 5.31.

 

The deprecated APIs are:

 

All APIs associated with the DEV driver interface. Developers are recommended to use the IOM driver interface.

 

DEV_createDevice

DEV_deleteDevice

DEV_match

Dxx_close

Dxx_ctrl

Dxx_idle

Dxx_init

Dxx_issue

Dxx_open

Dxx_ready

Dxx_reclaim

DGN Driver

DGS Driver

DHL Driver

 

All APIs associated with the PIP module. Developers are recommended to use the SIO module.

 

PIP_alloc

PIP_free

PIP_get

PIP_getReaderAddr

PIP_getReaderNumFrames

PIP_getReaderSize

PIP_getWriterAddr

PIP_getWriterNumFrames

PIP_getWriterSize

PIP_peek

PIP_put                                                                                        

PIP_reset

PIP_setWriterSize

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_31.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.31.00.01 with directory  bios_5_31_00_01) and the final release will be bios_5_31 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.31.03 with directory bios_5_31_03.  

Point releases where new features such as additional device support are released same as major baselines, i.e., with patch counter of zero and removed from directory qualifier, ex. 5.31 with directory bios_5_31.  When referring to the release, the term bios "five dot thirty-one" generally refers to the baseline bios 5.31 and the patches (ex. 5.31.03) and point releases (ex. 5.32) that comprise the compatible group.



 

DSP/BIOS v5.31.02 Release Notes

 

Last updated:  14 Nov 2006

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Known Issues", "Fixed In This Release", and "Validation Info".   

Check the following web site for updates: https://www-a.ti.com/downloads/sds_support/targetcontent/bios/index.html

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package
  DSP/BIOS Kernel Benchmarks
  XDC Tools (Tconf) Package
  DSP/BIOS Platforms
  DSP/BIOS Examples
  Real Time Data Exchange (RTDX)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support)
  DSP/BIOS Help Files
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD)
  DSP/BIOS Graphical Configuration Tool (Gconf)

General Information

DSP/BIOS 5.31.02 is an All ISA release and can be used with CCS 3.2, CCS 3.3 or later. This will be installed in <installdir>/bios_5_31_02.

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.31.02

Device Support

     
  Devices Supported* Runtime model
 

*BIOS Configuration DeviceName listed

 
     
28xx Devices    
  F2801
F2806
F2808
F2810
F2811
F2812
 
Large model
     
54xx Devices    
 
5402
5402A
5409A
5416
5470
5471
5405
 
Near and Far model supported
     
55xx Devices    
 

5501
5502
5503
5507
5509A
DA255
5510
5510A
5561

 

Large model on Laijin 2.x core devices

Note: 55xx small model support has been dropped starting with BIOS 5.10

 

5903 (OMAP)
5905
(OMAP)

5910 (OMAP)
5912 (OMAP)

5948 (OMAP)
5946 (OMAP)
5944 (OMAP)


1510 (OMAP)
1610 (OMAP)
1710 (OMAP)
2320 (OMAP)
2420 (OMAP)
 

TNETV1050 (Titan)
TNETV1055

Large model for 55xx DSP side of Heterogeneous multi processors (OMAP: ARM + 55xx DSP, Titan: MIPS + 55xx DSP)

Large and Huge model for 55xx DSP on Laijin 2.x/3.x, such as OMAP1710, OMAP2420

Note: 55xx small model support has been dropped starting with BIOS 5.10

     
62xx Devices    
  Not Supported: C6201
6202
6203
6204
6205
6211

 

Big and Little Endian
     
67xx Devices    
6701
6711
6711 - 250
6712
6713
6713 - 300
 

DA705 (Antara)
DA707
DA710
 

 

Big and Little Endian
     
64xx Devices    
  6410
6411
6412
6413
6414
6415
6416
6418
DRI300
DM640
DM641
DM642
Big and Little Endian
     
64P  Devices    

DM420
DM415
DM425
DM426

DM647

DM648

 

DM6431
DM6433
DM6435

DM6437
DM6443
DM6446

 

6421
6424
6452
6455
6454

 

TCI6482

TCI6486
TCI6487
TCI6488

 

DRA442
DRA446

 


2430 (OMAP)
3430 (OMAP)

Big and Little Endian
     
67P  Devices    
  6727 Little Endian
     
IAG Devices    
  DM270
DM310
DM320

DM420
DA300
DA295

 

Known Issues

    Please check the following link for additional information when upgrading from 4.90 to 5.x -- Knowledge base with known 4.90 to 5.x upgrade issues

    Davinci 1.x IDMA0 problem workaround -- A custom version of the HWI dispatcher was created to  work around an IDMA0/MMR problem in rev 1.x DM644x devices (see SPRZ241 - "TMS320DM6446 Digital Media System-on-chip Silicon Errata" for more information about this errata).  This errata is only present in Rev 1.x DM644x devices and is not present on other 64x+ devices.
 The HWI dispatcher has been updated to poll the IDMA0 status register and wait for IDMA0 transfer to complete before calling the actual ISR.  This will ensure that the ISR will not reference an MMR register while the IDMA0 is active.  This will also ensure that an asynchronous task switch will not occur while the IDMA0 is active.  This may affect interrupt response time, but should not be a problem in most applications since IDMA0 jobs are usually fairly short.  This workaround is only supported by the HWI dispatcher (the HWI_enter/exit macros do not contain the workaround).
 A hidden configuration parameter (bios.GBL.USEIDMA0DISPATCHER) is used to select this alternate version of the dispatcher.  This parameter has default value 'true' for DM644x and DM42x configurations.  This parameter has default value 'false' for all other 64x+ configurations.  The user can set this parameter to 'false' if they do not want this workaround used in their Davinci applications (e.g., if their application is not using IDMA0 and/or they know that that their ISRs do not reference MMR registers).

    Memory heap issue when updating  existing configuration files -- Prior versions of the configuration tool allowed for an inconsistent memory heap configuration.   The tool allowed users to enable heaps when no heaps were actually configured and the default for bios.MEM.MALLOCSEG and bios.MEM.SEGZERO were still set to 'MEM_NULL'.  This was causing problems in applications since malloc() and MEM_alloc() were failing even when user thought they had configured BIOS for dynamic memory allocation.  The configuration tool is now checking to make sure that configurations that have heaps also have bios.MEM.MALLOCSEG and bios.MEM.SEGZERO set to a valid heap.  Update from existing projects might yield an error message.  The work around is to either remove the 'bios.enableMemoryHeaps(prog);' line from your configuration, or to add a heap and set bios.MEM.MALLOCSEG and bios.MEM.SEGZERO accordingly.  See the ti/bios/examples/common/evmDM6446_common.tci file (or others) for an example of how to do this.

    RTA/RTDX problem when load/run different programs -- After running RTA successfully on a DaVinci program, if another program is then loaded without restarting CCS 3.2 then RTA may not work sometimes.  This problem is intermittent.  If displays do not update, the workaround is to restart CCS before loading a new program.  This is tracked by SDSCM00003318.

    DSP/BIOS RTA plugins update very slowly via RTDX on DaVinci -- (CCS 3.2 issue) When RTA plugins are opened after a program is loaded and started. To work around this problem, open the DSP/BIOS RTA plugins before starting the program. This is tracked by SDSCM00002472

   Gconf uses wrong parameters when more than one pjt is opened and they share the same .tcf file -- When more than one CCS project (.pjt file) share the same .tcf file, and two or more of the projects are opened in CCS, opening a .tcf from one of the projects will launch GConf using the DspBiosBuilder builder parameters defined for the most recently opened project. This may result in incorrect base seed properties and import file paths in the .tcf file being edited. To workaround, do not share .tcf files between projects. This is tracked by SDSCM00003834

  BIOS RTA has problems reading data in stop mode for some 64x+ devices -- Currently, stop mode reads will only work for DaVinci. This is tracked by SDSCM00010400

    DSP/BIOS examples that are using RTA halt when run every other time on DSK5510/DSK5509A via XDS560. This is tracked by SDSCM00005820.

    DSP/BIOS does not create a reset vector at address 0x800000 for TCI6482 or dsk6455. This is tracked by SDSCM00010342.

    CCS window closes on refreshing KOV Window when it receives illegal values -- KOV will crash if Module Objects have illegal values. For e.g if a dynamic task has a bad name, KOV will try to print the illegal name and crash. This is tracked by SDSCM00006694.   

    KOV window shows wrong names for dynamic objects -- This is tracked by SDSCM00007151.

    KOV displays wrong names for memory sections -- This is tracked by SDSCM00004917.

    Incorrect platform name in Tconf User's Guide in "Create New Platform" section -- The spru0007h.pdf document contains the correct instructions for creating a new platform using the Tconf's User's Guide, the help files were not updated to reflect the same naming convention. This is tracked by SDSCM00003471.

    RTDX error comes up on Debug -> Run when executing examples on 5912 via XDS 510 -- This is tracked by SDSSCM00005600.

    RTDX tutorial examples do not all execute as expected  when run on TCI6482 simulator little endian -- This is tracked by SDSSCM00010736.

    RTDX Hot-Connect does not work for C64P -- This is tracked by SDSSCM00011954.

    RTA (VBD) crash after lots of disconnects and connects -- This is tracked by SDSSCM00012471.

Fixed In This Release

The following bugs and enhancements have been fixed in this release.  These are also listed in the sub-component release notes, but provided here for convenience.

id Headline
SDSCM00013408 DSP/BIOS installer does not set RTDX paths correctly in registry

Validation Information

Codegen versions used in BIOS 5.31.02 product validation. See kernel release notes for the compiler versions used to build the target content.

ISA

Compiler version(s)

c6x v6.0.1, v6.0.5, v6.0.7
c55x v3.3.1, v3.3.2
c54x v4.1.0
c28x v4.1.0, v4.1.3

 

Deprecation Notice

 

Deprecated DSP/BIOS APIs: Some DSP/BIOS APIs are being deprecated and will no longer be supported in the next major release of DSP/BIOS.

These APIs are still supported in DSP/BIOS 5.31.02 and will be supported in any patch releases or minor enhancements to DSP/BIOS 5.31.

 

The deprecated APIs are:

 

All APIs associated with the DEV driver interface. Developers are recommended to use the IOM driver interface.

 

DEV_createDevice

DEV_deleteDevice

DEV_match

Dxx_close

Dxx_ctrl

Dxx_idle

Dxx_init

Dxx_issue

Dxx_open

Dxx_ready

Dxx_reclaim

DGN Driver

DGS Driver

DHL Driver

 

All APIs associated with the PIP module. Developers are recommended to use the SIO module.

 

PIP_alloc

PIP_free

PIP_get

PIP_getReaderAddr

PIP_getReaderNumFrames

PIP_getReaderSize

PIP_getWriterAddr

PIP_getWriterNumFrames

PIP_getWriterSize

PIP_peek

PIP_put                                                                                        

PIP_reset

PIP_setWriterSize

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_31.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.31.00.01 with directory  bios_5_31_00_01) and the final release will be bios_5_31 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.31.02 with directory bios_5_31_02.  

Point releases where new features such as additional device support are released same as major baselines, i.e., with patch counter of zero and removed from directory qualifier, ex. 5.31 with directory bios_5_31.  When referring to the release, the term bios "five dot thirty-one" generally refers to the baseline bios 5.31 and the patches (ex. 5.31.02) and point releases (ex. 5.32) that comprise the compatible group.

 



 

 

DSP/BIOS v5.31.01 Release Notes

 

Last updated:  06 Oct 2006

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Known Issues", "Fixed In This Release", and "Validation Info".   

Check the following web site for updates: https://www-a.ti.com/downloads/sds_support/targetcontent/bios/index.html

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package (updated)
  DSP/BIOS Kernel Benchmarks
  XDC Tools (Tconf) Package (updated)
  DSP/BIOS Platforms (updated)
  DSP/BIOS Examples (updated)
  Real Time Data Exchange (RTDX) (updated)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support)
  DSP/BIOS Help Files
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD) (updated)
  DSP/BIOS Graphical Configuration Tool (Gconf)

General Information

DSP/BIOS 5.31.01 is an All ISA release and can be used with CCS 3.2, CCS 3.3 or later. This will be installed in <installdir>/bios_5_31_01.

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.31.01

Device Support

     
  Devices Supported* Runtime model
 

*BIOS Configuration DeviceName listed

 
     
28xx Devices    
  F2801
F2806
F2808
F2810
F2811
F2812
 
Large model
     
54xx Devices    
 
5402
5402A
5409A
5416
5470
5471
5405
 
Near and Far model supported
     
55xx Devices    
 

5501
5502
5503
5507
5509A
DA255
5510
5510A
5561

 

Large model on Laijin 2.x core devices

Note: 55xx small model support has been dropped starting with BIOS 5.10

 

5903 (OMAP)
5905
(OMAP)

5910 (OMAP)
5912 (OMAP)

5948 (OMAP)
5946 (OMAP)
5944 (OMAP)


1510 (OMAP)
1610 (OMAP)
1710 (OMAP)
2320 (OMAP)
2420 (OMAP)
 

TNETV1050 (Titan)
TNETV1055

Large model for 55xx DSP side of Heterogeneous multi processors (OMAP: ARM + 55xx DSP, Titan: MIPS + 55xx DSP)

Large and Huge model for 55xx DSP on Laijin 2.x/3.x, such as OMAP1710, OMAP2420

Note: 55xx small model support has been dropped starting with BIOS 5.10

     
62xx Devices    
  Not Supported: C6201
6202
6203
6204
6205
6211

 

Big and Little Endian
     
67xx Devices    
6701
6711
6711 - 250
6712
6713
6713 - 300
 

DA705 (Antara)
DA707
DA710
 

 

Big and Little Endian
     
64xx Devices    
  6410
6411
6412
6413
6414
6415
6416
6418
DRI300
DM640
DM641
DM642
Big and Little Endian
     
64P  Devices    

DM420
DM415
DM425
DM426

DM647

DM648

 

DM6431
DM6433
DM6435

DM6437
DM6443
DM6446

 

6421
6424
6452
6455
6454

 

TCI6482

TCI6486
TCI6487
TCI6488

 

DRA442
DRA446

 


2430 (OMAP)
3430 (OMAP)

Big and Little Endian
     
67P  Devices    
  6727 Little Endian
     
IAG Devices    
  DM270
DM310
DM320

DM420
DA300
DA295

 

Known Issues

    Davinci 1.x IDMA0 problem workaround -- A custom version of the HWI dispatcher was created to  work around an IDMA0/MMR problem in rev 1.x DM644x devices (see SPRZ241 - "TMS320DM6446 Digital Media System-on-chip Silicon Errata" for more information about this errata).  This errata is only present in Rev 1.x DM644x devices and is not present on other 64x+ devices.
 The HWI dispatcher has been updated to poll the IDMA0 status register and wait for IDMA0 transfer to complete before calling the actual ISR.  This will ensure that the ISR will not reference an MMR register while the IDMA0 is active.  This will also ensure that an asynchronous task switch will not occur while the IDMA0 is active.  This may affect interrupt response time, but should not be a problem in most applications since IDMA0 jobs are usually fairly short.  This workaround is only supported by the HWI dispatcher (the HWI_enter/exit macros do not contain the workaround).
 A hidden configuration parameter (bios.GBL.USEIDMA0DISPATCHER) is used to select this alternate version of the dispatcher.  This parameter has default value 'true' for DM644x and DM42x configurations.  This parameter has default value 'false' for all other 64x+ configurations.  The user can set this parameter to 'false' if they do not want this workaround used in their Davinci applications (e.g., if their application is not using IDMA0 and/or they know that that their ISRs do not reference MMR registers).

    Memory heap issue when updating  existing configuration files -- Prior versions of the configuration tool allowed for an inconsistent memory heap configuration.   The tool allowed users to enable heaps when no heaps were actually configured and the default for bios.MEM.MALLOCSEG and bios.MEM.SEGZERO were still set to 'MEM_NULL'.  This was causing problems in applications since malloc() and MEM_alloc() were failing even when user thought they had configured BIOS for dynamic memory allocation.  The configuration tool is now checking to make sure that configurations that have heaps also have bios.MEM.MALLOCSEG and bios.MEM.SEGZERO set to a valid heap.  Update from existing projects might yield an error message.  The work around is to either remove the 'bios.enableMemoryHeaps(prog);' line from your configuration, or to add a heap and set bios.MEM.MALLOCSEG and bios.MEM.SEGZERO accordingly.  See the ti/bios/examples/common/evmDM6446_common.tci file (or others) for an example of how to do this.

    RTA/RTDX problem when load/run different programs -- After running RTA successfully on a DaVinci program, if another program is then loaded without restarting CCS 3.2 then RTA may not work sometimes.  This problem is intermittent.  If displays do not update, the workaround is to restart CCS before loading a new program.  This is tracked by SDSCM00003318.

    DSP/BIOS RTA plugins update very slowly via RTDX on DaVinci -- (CCS 3.2 issue) When RTA plugins are opened after a program is loaded and started. To work around this problem, open the DSP/BIOS RTA plugins before starting the program. This is tracked by SDSCM00002472

   Gconf uses wrong parameters when more than one pjt is opened and they share the same .tcf file -- When more than one CCS project (.pjt file) share the same .tcf file, and two or more of the projects are opened in CCS, opening a .tcf from one of the projects will launch GConf using the DspBiosBuilder builder parameters defined for the most recently opened project. This may result in incorrect base seed properties and import file paths in the .tcf file being edited. To workaround, do not share .tcf files between projects. This is tracked by SDSCM00003834

  BIOS RTA has problems reading data in stop mode for some 64x+ devices -- Currently, stop mode reads will only work for DaVinci. This is tracked by SDSCM00010400

    DSP/BIOS examples that are using RTA halt when run every other time on DSK5510/DSK5509A via XDS560. This is tracked by SDSCM00005820.

    DSP/BIOS does not create a reset vector at address 0x800000 for TCI6482 or dsk6455. This is tracked by SDSCM00010342.

    CCS window closes on refreshing KOV Window when it receives illegal values -- KOV will crash if Module Objects have illegal values. For e.g if a dynamic task has a bad name, KOV will try to print the illegal name and crash. This is tracked by SDSCM00006694.   

    KOV window shows wrong names for dynamic objects -- This is tracked by SDSCM00007151.

    KOV displays wrong names for memory sections -- This is tracked by SDSCM00004917.

    Incorrect platform name in Tconf User's Guide in "Create New Platform" section -- The spru0007h.pdf document contains the correct instructions for creating a new platform using the Tconf's User's Guide, the help files were not updated to reflect the same naming convention. This is tracked by SDSCM00003471.

    RTDX error comes up on Debug -> Run when executing examples on 5912 via XDS 510 -- This is tracked by SDSSCM00005600.

    RTDX tutorial examples do not all execute as expected  when run on TCI6482 simulator little endian -- This is tracked by SDSSCM00010736.

    RTDX Hot-Connect does not work for C64P -- This is tracked by SDSSCM00011954.

Fixed In This Release

The following bugs and enhancements have been fixed in this release.  These are also listed in the sub-component release notes, but provided here for convenience.

id Headline
SDSCM00003180 Flash plugin error: BIOS version is not compatible with RTA
SDSCM00003322 BCACHE/2430 should do dummy read after writeback/wait to ensure data has been completely written back
SDSCM00010300 big endian should not be an option for OMAP3430
SDSCM00010460 Resource special handler functions needs typedef
SDSCM00010747 Typo on SPRU403: C example code of C64_enableIER function
SDSCM00011053 The wugen event mask is lost during pwrm retention mode.
SDSCM00011055 DSP stuck in idle state after early wake-up event.
SDSCM00011213 TCF file does not open in environment of DSK5509
SDSCM00011276 Latency example has incorrect parameter to main
SDSCM00011678 SK library missing from BIOS 5.31
SDSCM00011892 memory maps in catalog files for LC are incorrect for L1P/D and L2
SDSCM00011933 Bogus exception generated on C64x+ HW, affecting BIOS EXC module
SDSCM00012114 Add 'far' to BCACHE_bootInit() prototype in boot.c to avoid trampoline problem
SDSCM00012191 Real MSGQ constraints are not documented
SDSCM00012243 BIOS HWI module does not enable exceptions (TSR.XEN)
SDSCM00012246 BIOS EXC processing should not use existing SP (B15) if not a system trap (SWE instruction)

Validation Information

Codegen versions used in BIOS 5.31_01 product validation. See kernel release notes for the compiler versions used to build the target content.

ISA

Compiler version(s)

c6x v6.0.1, v6.0.5
c55x v3.3.1, v3.3.2
c54x v4.1.0
c28x v4.1.0, v4.1.3

 

Deprecation Notice

 

Deprecated DSP/BIOS APIs: Some DSP/BIOS APIs are being deprecated and will no longer be supported in the next major release of DSP/BIOS.

These APIs are still supported in DSP/BIOS 5.31.01 and will be supported in any patch releases or minor enhancements to DSP/BIOS 5.31.

 

The deprecated APIs are:

 

All APIs associated with the DEV driver interface. Developers are recommended to use the IOM driver interface.

 

DEV_createDevice

DEV_deleteDevice

DEV_match

Dxx_close

Dxx_ctrl

Dxx_idle

Dxx_init

Dxx_issue

Dxx_open

Dxx_ready

Dxx_reclaim

DGN Driver

DGS Driver

DHL Driver

 

All APIs associated with the PIP module. Developers are recommended to use the SIO module.

 

PIP_alloc

PIP_free

PIP_get

PIP_getReaderAddr

PIP_getReaderNumFrames

PIP_getReaderSize

PIP_getWriterAddr

PIP_getWriterNumFrames

PIP_getWriterSize

PIP_peek

PIP_put                                                                                        

PIP_reset

PIP_setWriterSize

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_31.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.31.00.01 with directory  bios_5_31_00_01) and the final release will be bios_5_31 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.31.01 with directory bios_5_31_01.  

Point releases where new features such as additional device support are released same as major baselines, i.e., with patch counter of zero and removed from directory qualifier, ex. 5.31 with directory bios_5_31.  When referring to the release, the term bios "five dot thirty-one" generally refers to the baseline bios 5.31 and the patches (ex. 5.31.01) and point releases (ex. 5.32) that comprise the compatible group.

 



 

DSP/BIOS v5.31 Release Notes

 

Last updated:  08 Aug 2006

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Known Issues", "Fixed In This Release", and "Validation Info".   

Check the following web site for updates: https://www-a.ti.com/downloads/sds_support/targetcontent/bios/index.html

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package (updated)
  DSP/BIOS Kernel Benchmarks (updated)
  XDC Tools (Tconf) Package (updated)
  DSP/BIOS Platforms (updated)
  DSP/BIOS Examples (updated)
  Real Time Data Exchange (RTDX) (updated)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support) (updated)
  DSP/BIOS Help Files (updated)
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD)
  DSP/BIOS Graphical Configuration Tool (Gconf) (updated)

General Information

DSP/BIOS 5.31 is an All ISA release and can be used with CCS 3.2, CCS 3.3 or later. This will be installed in <installdir>/bios_5_31.

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.31

Device Support

     
  Devices Supported* Runtime model
 

*BIOS Configuration DeviceName listed

 
     
28xx Devices    
  F2801
F2806
F2808
F2810
F2811
F2812
 
Large model
     
54xx Devices    
 
5402
5402A
5409A
5416
5470
5471
5405
 
Near and Far model supported
     
55xx Devices    
 

5501
5502
5503
5507
5509A
DA255
5510
5510A
5561

 

Large model on Laijin 2.x core devices

Note: 55xx small model support has been dropped starting with BIOS 5.10

 

5903 (OMAP)
5905
(OMAP)

5910 (OMAP)
5912 (OMAP)

5948 (OMAP)
5946 (OMAP)
5944 (OMAP)


1510 (OMAP)
1610 (OMAP)
1710 (OMAP)
2320 (OMAP)
2420 (OMAP)
 

TNETV1050 (Titan)
TNETV1055

Large model for 55xx DSP side of Heterogeneous multi processors (OMAP: ARM + 55xx DSP, Titan: MIPS + 55xx DSP)

Large and Huge model for 55xx DSP on Laijin 2.x/3.x, such as OMAP1710, OMAP2420

Note: 55xx small model support has been dropped starting with BIOS 5.10

     
62xx Devices    
  Not Supported: C6201
6202
6203
6204
6205
6211

 

Big and Little Endian
     
67xx Devices    
6701
6711
6711 - 250
6712
6713
6713 - 300
 

DA705 (Antara)
DA707
DA710
 

 

Big and Little Endian
     
64xx Devices    
  6410
6411
6412
6413
6414
6415
6416
6418
DRI300
DM640
DM641
DM642
Big and Little Endian
     
64P  Devices    

DM420
DM415
DM425
DM426

DM647

 

DM6431
DM6433
DM6435

DM6437
DM6443
DM6446

 

6421
6424
6452
6455
6454

 

TCI6482

TCI6486
TCI6487
TCI6488

 

DRA442
DRA446

 


2430 (OMAP)
3430 (OMAP)

Big and Little Endian
     
67P  Devices    
  6727 Little Endian
     
IAG Devices    
  DM270
DM310
DM320

DM420
DA300
DA295

 

Known Issues

    Davinci 1.x IDMA0 problem workaround -- A custom version of the HWI dispatcher was created to  work around an IDMA0/MMR problem in rev 1.x DM644x devices (see SPRZ241 - "TMS320DM6446 Digital Media System-on-chip Silicon Errata" for more information about this errata).  This errata is only present in Rev 1.x DM644x devices and is not present on other 64x+ devices.
 The HWI dispatcher has been updated to poll the IDMA0 status register and wait for IDMA0 transfer to complete before calling the actual ISR.  This will ensure that the ISR will not reference an MMR register while the IDMA0 is active.  This will also ensure that an asynchronous task switch will not occur while the IDMA0 is active.  This may affect interrupt response time, but should not be a problem in most applications since IDMA0 jobs are usually fairly short.  This workaround is only supported by the HWI dispatcher (the HWI_enter/exit macros do not contain the workaround).
 A hidden configuration parameter (bios.GBL.USEIDMA0DISPATCHER) is used to select this alternate version of the dispatcher.  This parameter has default value 'true' for DM644x and DM42x configurations.  This parameter has default value 'false' for all other 64x+ configurations.  The user can set this parameter to 'false' if they do not want this workaround used in their Davinci applications (e.g., if their application is not using IDMA0 and/or they know that that their ISRs do not reference MMR registers).

    Memory heap issue when updating  existing configuration files -- Prior versions of the configuration tool allowed for an inconsistent memory heap configuration.   The tool allowed users to enable heaps when no heaps were actually configured and the default for bios.MEM.MALLOCSEG and bios.MEM.SEGZERO were still set to 'MEM_NULL'.  This was causing problems in applications since malloc() and MEM_alloc() were failing even when user thought they had configured BIOS for dynamic memory allocation.  The configuration tool is now checking to make sure that configurations that have heaps also have bios.MEM.MALLOCSEG and bios.MEM.SEGZERO set to a valid heap.  Update from existing projects might yield an error message.  The work around is to either remove the 'bios.enableMemoryHeaps(prog);' line from your configuration, or to add a heap and set bios.MEM.MALLOCSEG and bios.MEM.SEGZERO accordingly.  See the ti/bios/examples/common/evmDM6446_common.tci file (or others) for an example of how to do this.

    BCACHE_wb()/OMAP2430 Problem -- BCACHE_wb() and BCACHE_wbInv() implementation for the OMAP2430 does not contain extra logic to ensure that the data has reached the destination memory before the 'wait' returns.  The cache registers correctly indicate that the data has been written from the cache to memory, but there may be additional delay before the data reaches its final destination memory.  This may be a problem when this memory is accessed by another CPU or peripheral before the final write has completed.  The workaround is to do dummy read of the last word of the buffer passed to BCACHE_wb() since this read will not complete until the writeback has completed.  This is not a problem for Davinci, 6455 or TCI6482 implementation which contain extra logic to ensure that the 'wait' does not return until the destination memory has been completely updated.  This is tracked by SDSCM00003322.

    RTA/RTDX problem when load/run different programs -- After running RTA successfully on a DaVinci program, if another program is then loaded without restarting CCS 3.2 then RTA may not work sometimes.  This problem is intermittent.  If displays do not update, the workaround is to restart CCS before loading a new program.  This is tracked by SDSCM00003318.

    DSP/BIOS RTA plugins update very slowly via RTDX on DaVinci -- (CCS 3.2 issue) When RTA plugins are opened after a program is loaded and started. To work around this problem, open the DSP/BIOS RTA plugins before starting the program. This is tracked by SDSCM00002472

   Gconf uses wrong parameters when more than one pjt is opened and they share the same .tcf file -- When more than one CCS project (.pjt file) share the same .tcf file, and two or more of the projects are opened in CCS, opening a .tcf from one of the projects will launch GConf using the DspBiosBuilder builder parameters defined for the most recently opened project. This may result in incorrect base seed properties and import file paths in the .tcf file being edited. To workaround, do not share .tcf files between projects. This is tracked by SDSCM00003834

  BIOS RTA has problems reading data in stop mode for some 64x+ devices -- Currently, stop mode reads will only work for DaVinci. This is tracked by SDSCM00010400

    DSP/BIOS examples that are using RTA halt when run every other time on DSK5510/DSK5509A via XDS560. This is tracked by SDSCM00005820.

    CCS window closes on refreshing KOV Window when it receives illegal values -- KOV will crash if Module Objects have illegal values. For e.g if a dynamic task has a bad name, KOV will try to print the illegal name and crash. This is tracked by SDSCM00006694.   

    KOV window shows wrong names for dynamic objects -- This is tracked by SDSCM00007151.

    KOV displays wrong names for memory sections -- This is tracked by SDSCM00004917.

    Incorrect platform name in Tconf User's Guide in "Create New Platform" section -- The spru0007h.pdf document contains the correct instructions for creating a new platform using the Tconf's User's Guide, the help files were not updated to reflect the same naming convention. This is tracked by SDSCM00003471.

    RTDX error comes up on Debug -> Run when executing examples on 5912 via XDS 510 -- This is tracked by SDSSCM00005600.

Fixed In This Release

The following bugs and enhancements have been fixed in this release.  These are also listed in the sub-component release notes, but provided here for convenience.

id Headline
SDSCM00003321 EXC exception handler not calling SYS_abort correctly
SDSCM00003849 Message Log updated incorrectly for Mem_Management/SWI
SDSCM00003850 Message Log updating Issue with CLK and HELLO example
SDSCM00006878 Message log is not updated for MPC examples on evmDM6446
SDSCM00007169  Bug in PWRM_init can cause BIOS init failures on C64x+
SDSCM00007313 RTDX still being built w/ far code, far data
SDSCM00007348 Documentation error in sleep example.
SDSCM00007452 CLK ISR, CLK functions, and PRDs can still run following a call to CLK_stop()
SDSCM00007508 Enhance HWI_dispatchPlug to not plug the IST if the interrupt is already configured for the HWI dispatcher
SDSCM00007574 BIOS for omap3430 not initializing the timer correctly
SDSCM00007580 bios.setMemCodeSections silently fails when not able to set segments correctly
SDSCM00007643 Utility Programs chapter should be pulled from BIOS API guide
SDSCM00007677 Proper rts library file is not linked when compiled tconf file for 6713
SDSCM00007812 Text of DSP/BIOS help pages refer to old version of DSP/BIOS
SDSCM00007893 TConfCmdObject should add RTDX link path when updating a BIOS 4.x project to BIOS 5.x
SDSCM00008003 3430: GP timers 7 and 8 available in CLK selection drop down box, but cannot be selected because "interrupts not mapped"
SDSCM00008030 Heap is not allocated properly when "Reuse startup code space" is checked
SDSCM00008048 Error in automated TConf script in DSP/BIOS examples
SDSCM00008088 DSP/BIOS tutorial steps for Creating a Simple Application are incorrect
SDSCM00008131 DSP/BIOS does the register PERLOCK and PERCFG0 intialization which user should be doing
SDSCM00009838 Need update to HWI_dispatchPlug API description for C6x devices
SDSCM00009840 672x big endian libraries should be removed from Bios, Si does not support it.
SDSCM00009931 TConfCmdObject does not handle case sensitive cdb file correctly when checking for conversion to tcf
SDSCM00010007 bios.setMemDataNoHeapSections needs to handle PWRM fields for OMAP3430 (and others??)
SDSCM00010122 Notify clients of target state upon target connect
SDSCM00010204 TSK_delete() must free TSK_Obj before task stack to keep KOV (and user switch hooks) happy

SDSCM00010426

GConf uses latest DspBiosBuilder options when more than one project is opened and the projects are in the same directory
SDSCM00010796 BCACHE_wait() may write to address '0' causing memory violation

Validation Information

Codegen versions used in BIOS 5.31 product validation. See kernel release notes for the compiler versions used to build the target content.

ISA

Compiler version(s)

c6x v6.0.1, v6.0.4
c55x v3.3.1, v3.3.2
c54x v4.1.0
c28x v4.1.0, v4.1.3

 

Deprecation Notice

 

Deprecated DSP/BIOS APIs: Some DSP/BIOS APIs are being deprecated and will no longer be supported in the next major release of DSP/BIOS.

These APIs are still supported in DSP/BIOS 5.31 and will be supported in any patch releases or minor enhancements to DSP/BIOS 5.31.

 

The deprecated APIs are:

 

All APIs associated with the DEV driver interface. Developers are recommended to use the IOM driver interface.

 

DEV_createDevice

DEV_deleteDevice

DEV_match

Dxx_close

Dxx_ctrl

Dxx_idle

Dxx_init

Dxx_issue

Dxx_open

Dxx_ready

Dxx_reclaim

DGN Driver

DGS Driver

DHL Driver

 

All APIs associated with the PIP module. Developers are recommended to use the SIO module.

 

PIP_alloc

PIP_free

PIP_get

PIP_getReaderAddr

PIP_getReaderNumFrames

PIP_getReaderSize

PIP_getWriterAddr

PIP_getWriterNumFrames

PIP_getWriterSize

PIP_peek

PIP_put                                                                                        

PIP_reset

PIP_setWriterSize

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_31.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.31.00.01 with directory  bios_5_31_00_01) and the final release will be bios_5_31 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.31.01 with directory bios_5_31_01.  

Point releases where new features such as additional device support are released same as major baselines, i.e., with patch counter of zero and removed from directory qualifier, ex. 5.31 with directory bios_5_31.  When referring to the release, the term bios "five dot thirty-one" generally refers to the baseline bios 5.31 and the patches (ex. 5.31.01) and point releases (ex. 5.32) that comprise the compatible group.

 



 

DSP/BIOS v5.30 Release Notes

 

Last updated: 14 Jun 2006

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Known Issues", "Fixed In This Release", and "Validation Info".   

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package (updated)
  DSP/BIOS Kernel Benchmarks (updated)
  XDC Tools (Tconf) Package (updated)
  DSP/BIOS Platforms (updated)
  DSP/BIOS Examples (updated)
  Real Time Data Exchange (RTDX) (updated)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support) (updated)
  DSP/BIOS Help Files (updated)
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD)
  DSP/BIOS Graphical Configuration Tool (Gconf) (updated)

General Information

DSP/BIOS 5.30 is an All ISA release and can be used with CCS 3.2, CCS 3.3 or later. This will be installed in <installdir>/bios_5_30.

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.30

Known Issues

    Davinci 1.x IDMA0 problem workaround -- A custom version of the HWI dispatcher was created to  work around an IDMA0/MMR problem in rev 1.x DM644x devices (see SPRZ241 - "TMS320DM6446 Digital Media System-on-chip Silicon Errata" for more information about this errata).  This errata is only present in Rev 1.x DM644x devices and is not present on other 64x+ devices.
 The HWI dispatcher has been updated to poll the IDMA0 status register and wait for IDMA0 transfer to complete before calling the actual ISR.  This will ensure that the ISR will not reference an MMR register while the IDMA0 is active.  This will also ensure that an asynchronous task switch will not occur while the IDMA0 is active.  This may affect interrupt response time, but should not be a problem in most applications since IDMA0 jobs are usually fairly short.  This workaround is only supported by the HWI dispatcher (the HWI_enter/exit macros do not contain the workaround).
 A hidden configuration parameter (bios.GBL.USEIDMA0DISPATCHER) is used to select this alternate version of the dispatcher.  This parameter has default value 'true' for DM644x and DM42x configurations.  This parameter has default value 'false' for all other 64x+ configurations.  The user can set this parameter to 'false' if they do not want this workaround used in their Davinci applications (e.g., if their application is not using IDMA0 and/or they know that that their ISRs do not reference MMR registers).

    Memory heap issue when updating  existing configuration files -- Prior versions of the configuration tool allowed for an inconsistent memory heap configuration.   The tool allowed users to enable heaps when no heaps were actually configured and the default for bios.MEM.MALLOCSEG and bios.MEM.SEGZERO were still set to 'MEM_NULL'.  This was causing problems in applications since malloc() and MEM_alloc() were failing even when user thought they had configured BIOS for dynamic memory allocation.  The configuration tool is now checking to make sure that configurations that have heaps also have bios.MEM.MALLOCSEG and bios.MEM.SEGZERO set to a valid heap.  Update from existing projects might yield an error message.  The work around is to either remove the 'bios.enableMemoryHeaps(prog);' line from your configuration, or to add a heap and set bios.MEM.MALLOCSEG and bios.MEM.SEGZERO accordingly.  See the ti/bios/examples/common/evmDM6446_common.tci file (or others) for an example of how to do this.

    RTA/RTDX problems on simulators -- Real time analysis (RTA) and RTDX are not reliable on the 64x+ simulators.  For some applications, a few LOG entries are not displayed and other applications have no LOG output at all.  This problem appears to be unique to the simulator since the same examples run fine on the sdp2430 or evm6446 boards.  These issues are tracked by SDSCM00003849, SDSCM00003850, SDSCM00003851 and SDSCM00006695.

    BCACHE_wb()/OMAP2430 Problem -- BCACHE_wb() and BCACHE_wbInv() implementation for the OMAP2430 does not contain extra logic to ensure that the data has reached the destination memory before the 'wait' returns.  The cache registers correctly indicate that the data has been written from the cache to memory, but there may be additional delay before the data reaches its final destination memory.  This may be a problem when this memory is accessed by another CPU or peripheral before the final write has completed.  The workaround is to do dummy read of the last word of the buffer passed to BCACHE_wb() since this read will not complete until the writeback has completed.  This is not a problem for Davinci, 6455 or TCI6482 implementation which contain extra logic to ensure that the 'wait' does not return until the destination memory has been completely updated.  This is tracked by SDSCM00003322.

    RTA/RTDX problem when load/run different programs -- After running RTA successfully on a DaVinci program, if another program is then loaded without restarting CCS 3.2 then RTA may not work sometimes.  This problem is intermittent.  If displays do not update, the workaround is to restart CCS before loading a new program.  This is tracked by SDSCM00003318.

    DSP/BIOS RTA plugins update very slowly via RTDX on DaVinci -- When RTA plugins are opened after a program is loaded and started. To work around this problem, open the DSP/BIOS RTA plugins before starting the program. This is tracked by SDSCM00002472

    DSP/BIOS examples that are using RTA halt when run every other time on DSK5510/DSK5509A via XDS560. This is tracked by SDSCM00005820.

    CCS window closes on refreshing KOV Window when it receives illegal values -- KOV will crash if Module Objects have illegal values. For e.g if a dynamic task has a bad name, KOV will try to print the illegal name and crash. This is tracked by SDSCM00006694.   

    KOV window shows wrong names for dynamic objects -- This is tracked by SDSCM00007151.

    KOV displays wrong names for memory sections -- This is tracked by SDSCM00004917.

    Incorrect platform name in Tconf User's Guide in "Create New Platform" section -- The spru0007h.pdf document contains the correct instructions for creating a new platform using the Tconf's User's Guide, the help files were not updated to reflect the same naming convention. This is tracked by SDSCM00003471.

    RTDX error comes up on Debug -> Run when executing examples on 5912 via XDS 510 -- This is tracked by SDSSCM00005600.

Fixed In This Release

The following bugs and enhancements have been fixed in this release.  These are also listed in the sub-component release notes, but provided here for convenience.

id Headline
SDSCM00001268 Help file shows incorrect number of buttons for new config
SDSCM00001419 Mailbox example in SABIOS for ezdsp2812 gives 57005 instead of 2 in Msg Size
SDSCM00002869 DSP/BIOS Config Run in Graphical Debugger fails to open .tcf file if spaces in pathname
SDSCM00002893 L1 cache configuration for c64+ devices is not complete
SDSCM00003277 BIOS install dialog title are "Panel *"
SDSCM00003313 MSGQ should allow anonymous queues
SDSCM00003321 EXC exception handler not calling SYS_abort correctly
SDSCM00003329 BIOS cache initialization for Joule/GEM needs to be done before cinit processing
SDSCM00003359 MPC library for omap2430 doesn't handle global addresses for local memories
SDSCM00003471 Incorrect platform name in Tconf User's Guide in "Create New Platform" section
SDSCM00003472 Project Update fails in CCStudio_v3.2 because of missing CDB files
SDSCM00003508 Linux and Solaris installs should be '.sh' (not '.bin') for InstallShieldX and later
SDSCM00003748 Need way to modify processor Id for BIOS application
SDSCM00003809 BIOS CLK_gethtime still has 'backwards movement' symptom
SDSCM00003813 Graphical Edit broken when target has older BIOS
SDSCM00003815 Broken links in BIOS help file
SDSCM00003816 separate load should be created for .hwi section
SDSCM00003818 Description for eZdsp2812 configuration seed file needs correction
SDSCM00003819 In eZdsp2812 configuration seed file, comment for OTP memory incorrect
SDSCM00003821 C2800 DSP/BIOS Should Limit Task Stack to Lower 64K Memory
SDSCM00003824 DSP/BIOS C28x Statistics View window showing negative values
SDSCM00003825 Application does not build for 5507 and 5503 when PWRM is being used.
SDSCM00003827 Update 4.90 cdb to bios 5.20 tcf fails when file open used for sim55xx
SDSCM00003828 TSK 'Stack Peak' value on KOV might not be correct if stacksize > 0x7FFF
SDSCM00003832 Stairstep example needs to get added to examples in sabios
SDSCM00003837 TNETV1050 CLK_gethtime() isn't bulletproof
SDSCM00003841 TSK_create should align user-supplied stack
SDSCM00003845 Gconf throws JavaScript Exception message and fails to save the tcf file
SDSCM00004066 BIOS config needs to support timer rate driven by external clock for Himalaya
SDSCM00004067 Bigtime has an error in millenium roll over
SDSCM00004265 BIOS 5.20.02.28 release notes do not match DDTS query for fixed bugs
SDSCM00004322 Update BIOS UG/API RG to mention support of anonymous message queues.
SDSCM00004326 LOG should allow >32K buffer sizes for 64x
SDSCM00004434 MEM_undefine and locks for MEM_(re)define for Bridge
SDSCM00004561 KOV causes CCS to hang for certain 54x programs
SDSCM00004662 remove PWRM from dm420.cdb file
SDSCM00004678 BIOS examples still not portable (makefile)
SDSCM00004873 Antara config should error if ROM selected for 5.30,  emove Antara/ROM libs, update examples!
SDSCM00004877 Initialization of reserved MARs 0-2 causing exception
SDSCM00004952 BCache creates un-necessary code footprint
SDSCM00004992 Remove all .set to float values
SDSCM00005101 GTconf does not take "macro.ini" into account
SDSCM00005102 BIOS shouldnt recommend tweaking product tci files
SDSCM00005104 6000 RTDX Header File rtdx_access.h Should Not Check Memoey Model
SDSCM00005106 RTDX RTDX_SetInterrupt Clears all IFR
SDSCM00005110 RTDX_access.h for c6x broken (refers to C55 compiler macros)
SDSCM00005469 __TMS320C55X_PLUS__ is always defined by assembler. std.h55 must use .if $isdefed and .if to define _55P_
SDSCM00005618 BIOS needs to allocate extra word for RTDX recieve buffer (HS-RTDX rx overrun)
SDSCM00005690 Need to document new BIOS MEM APis (undefine and increaseTableSize)
SDSCM00005721 latency example int14 monitor address incorrect for dsk6455 platform
SDSCM00005781 Remove support for HS-RTDX for 64+ and 67+
SDSCM00005792 Building issue with C6711 Cycle Accurate Sim Ltl Endian for volume example using volume.pjt file.
SDSCM00006290 SWI_enable/disable, TSK_enable/disable usage must be carefully managed.
SDSCM00006308 Tconf User Guide need updates for BIOS 5.30
SDSCM00006424 Gconf.exe platform listing shows too many platforms
SDSCM00006438 On Titan platform, lower 16 bits of PCNTL access register should not be written.
SDSCM00006442 C55x BIOS should clear SST in ST3 upon reset
SDSCM00006458 cdb2tcf fails to convert cdb to tcf file while opening a Bios4.9 pjt file
SDSCM00006467 New TConfCmdObject doesn't get registered
SDSCM00006492 RTA needs to set RTDX.dll buffer size to max frame size
SDSCM00006515 RTDX 28x libraries should be built with 4.1.3 or later codegen
SDSCM00006527 BIOS config should check that RTDX buffer size is greater tha RTA frame size
SDSCM00006545 IDMA0 bug workaround is required for HWI_dispatcher for Davinci
SDSCM00006581 Volume example : CPU load graph does not update according to given in help files
SDSCM00006799 BIOS Timer does not work on c6455 when no L1P cache

The following defects were fixed in 5.20.02 but were not mentioned in the release notes for that version.

Identifier Headline
SDSsq43312 Setting odd stack size (MAUs) for c55x causes error with RTDX
SDSsq43347 DSP/BIOS Benchmark errors
SDSsq43653 Cdb2tcf fails if there is a whitespace in the path
SDSsq43666 Sim64P latency example timer address is specific to dm420
SDSsq43962 CCS 3.1 hangs when examples run out of ROM on padk6727 and KOV open
SDSsq43063 CCS requires gconf to be registered in order to register it

 

Validation Information

Codegen versions used in BIOS 5.30 product validation. See kernel release notes for the compiler versions used to build the target content.

ISA

Compiler version(s)

c6x v6.0.1, v6.0.3
c55x v3.3.1, v3.3.2
c54x v4.1.0
c28x v4.1.0

 

Deprecation Notice

 

Deprecated DSP/BIOS APIs: Some DSP/BIOS APIs are being deprecated and will no longer be supported in the next major release of DSP/BIOS.

These APIs are still supported in DSP/BIOS 5.30 and will be supported in any patch releases or minor enhancements to DSP/BIOS 5.30.

 

The deprecated APIs are:

 

All APIs associated with the DEV driver interface. Developers are recommended to use the IOM driver interface.

 

DEV_createDevice

DEV_deleteDevice

DEV_match

Dxx_close

Dxx_ctrl

Dxx_idle

Dxx_init

Dxx_issue

Dxx_open

Dxx_ready

Dxx_reclaim

DGN Driver

DGS Driver

DHL Driver

 

All APIs associated with the PIP module. Developers are recommended to use the SIO module.

 

PIP_alloc

PIP_free

PIP_get

PIP_getReaderAddr

PIP_getReaderNumFrames

PIP_getReaderSize

PIP_getWriterAddr

PIP_getWriterNumFrames

PIP_getWriterSize

PIP_peek

PIP_put                                                                                        

PIP_reset

PIP_setWriterSize

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_30.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.30.00.01 with directory  bios_5_30_00_01) and the final release will be bios_5_30 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.30.01 with directory bios_5_30_01.  

Point releases where new features such as additional device support are released same as major baselines, i.e., with patch counter of zero and removed from directory qualifier, ex. 5.30 with directory bios_5_30.  When referring to the release, the term bios "five dot thirty" generally refers to the baseline bios 5.30 and the patches (ex. 5.30.01) and point releases (ex. 5.31) that comprise the compatible group.



 

 

DSP/BIOS v5.21 Release Notes

 

Last updated: 05 January 2006

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Known Issues", "Fixed In This Release", and "Validation Info".   

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package (updated)
  DSP/BIOS Kernel Benchmarks (updated)
  XDC Tools (Tconf) Package (updated)
  DSP/BIOS Platforms (updated)
  DSP/BIOS Examples (updated)
  Real Time Data Exchange (RTDX)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support)
  DSP/BIOS Help Files (updated)
  DSP/BIOS Build Tools Interface (BTI) for CCS (updated)
  Real Time Analysis Infrastructure (VBD) (updated)
  DSP/BIOS Graphical Configuration Tool (Gconf) (updated)

General Information

DSP/BIOS 5.21 is a 6x-only release and can only be used with CCS 3.2 or later.   Documentation for other devices is provided with this release, but no software is provided to support anything but 6x devices.  This will be installed in <installdir>/bios_5_21_pp_b (pp_b are optional and used for patch and build counter).

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.21

Known Issues

   evmDavinci platform replaced by evmDM6446 and evmDM420 -- The evmDavinci platform support files and examples have been removed from this release.  This has been replaced by evmDM420 and evmDM6446 platform support.  Examples for the evmDM6446 board are provided with this release.  If you are using evmDavinci platform from 5.20, you can change your .tcf file(s) to use 'utils.loadPlatform("ti.platforms.evmDM6446")' or 'utils.loadPlatform("ti.platforms.evmDM420")'.   The following changes were also made to these platforms: (1) the 'DDR' memory segment from evmDavinci was renamed to 'DDR2', and (2) the params.clockRate was changed from 594 to 486 to match the default CPU rate for the EVM boards (set via Linux UBOOT and/or Arm .gel file).

    Memory heap issue when updating  existing configuration files -- Prior versions of the configuration tool allowed for an inconsistent memory heap configuration.   The tool allowed users to enable heaps when no heaps were actually configured and the default for bios.MEM.MALLOCSEG and bios.MEM.SEGZERO were still set to 'MEM_NULL'.  This was causing problems in applications since malloc() and MEM_alloc() were failing even when user thought they had configured BIOS for dynamic memory allocation.  The configuration tool is now checking to make sure that configurations that have heaps also have bios.MEM.MALLOCSEG and bios.MEM.SEGZERO set to a valid heap.  Update from existing projects might yield an error message.  The work around is to either remove the 'bios.enableMemoryHeaps(prog);' line from your configuration, or to add a heap and set bios.MEM.MALLOCSEG and bios.MEM.SEGZERO accordingly.  See the ti/bios/examples/common/evmDM6446_common.tci file (or others) for an example of how to do this.

    RTA/RTDX problems on simulators -- Real time analysis (RTA) and RTDX are not reliable on the 64x+ simulators.  For some applications, a few LOG entries are not displayed and other applications have no LOG output at all.  This problem appears to be unique to the simulator since the same examples run fine on the sdp2430 or evm6446 boards.  These issues are tracked by SDSsq44620, SDSsq44630 and SDSsq44631.

    BCACHE_wb()/OMAP2430 Problem -- BCACHE_wb() and BCACHE_wbInv() implementation for the OMAP2430 does not contain extra logic to ensure that the data has reached the destination memory before the 'wait' returns.  The cache registers correctly indicate that the data has been written from the cache to memory, but there may be additional delay before the data reaches its final destination memory.  This may be a problem when this memory is accessed by another CPU or peripheral before the final write has completed.  The workaround is to do dummy read of the last word of the buffer passed to BCACHE_wb() since this read will not complete until the writeback has completed.  This is not a problem for Davinci, 6455 or TCI6482 implementation which contain extra logic to ensure that the 'wait' does not return until the destination memory has been completely updated.  This is tracked by SDSCM00003322.

    CACHE initialization is too late if L1D is used for initialized data -- DSP/BIOS initializes the cache within BIOS_init() which is called after .cinit processing.  The .cinit processing occurs in the function _auto_init(), and the DSP/BIOS cache configuration happens after the processing of .cinit records.  Since some .cinit records initialize data that has possibly been placed in L1D RAM, if that RAM is still configured as cache, L1D cache activity related to L2 or external memory accesses can potentially step on the initialization into L1D.  This problem occurs since the device boots with L1D and L1P in '32K mode' (L2 is '0K' at reset).  To workaround this, either make sure you don't have any initialized data in L1D, or set L1PCFG and L1DCFG (0x01840020 and 0x01840040) to '0' in a custom boot.c file that you link with your application.  This disables the L1P and L1D caches during boot.  See the ti/bios/examples/advanced/mpc*/boot.c for an example of the workaround.  This is tracked by SDSCM00003329.

    PATH inconsistent with CCS 3.2 beta -- The CCS 3.2 beta2 installation sets the "PATH" environment variable to point to the 'bios_5_20_03' directory since CCS 3.2 beta 2 contains BIOS 5.20.03.  This can cause problems if you are doing Windows builds from the command line.  This will not be a problem if you are doing builds using CCS .pjt files.  Make sure that your PATH and BIOS_INSTALL_DIR variables are both pointing to bios_5_21 (or whatever DSP/BIOS release you want to work with).  This is tracked by SDSCM00003316.

    RTA/RTDX problem when load/run different programs -- After running RTA successfully on a DaVinci program, if another program is then loaded without restarting CCS 3.2 then RTA may not work sometimes.  This problem is intermittent.  If displays do not update, the workaround is to restart CCS before loading a new program.  This is tracked by SDSCM00003318.

    MPC examples don't work on sdp2430 board -- The MPC examples don't work correctly for the sdp2430 board.  This is tracked by SDSCM00003359.

Fixed In This Release

The following bugs and enhancements have been fixed in this release.  These are also listed in the sub-component release notes, but provided here for convenience.

Identifier Headline
SDSsq29116 HWI dispatcher cache control fields should be unwritable for C6x1x DSPs
SDSsq37229 DSP BIOS 5.00 install gives vague message when out of space
SDSsq38132 SABIOS installation hangs up in certain Linux systems (e.g. RHEL 3)
SDSsq40713 Level 2 interrupt support needed for BIOS for Joule/GEM
SDSsq41788 Cannot reload volume4 executable through PDM
SDSsq42249 HWI_dispatchPlug needs support for selector for GEM cores
SDSsq42754 Can't use HWI_dispatchPlug() or C64_plug() if HWI vectors in L1P SRAM
SDSsq43117 Linux install does not fail if quota is exceeded
SDSsq43219 BIOS 5.10.01.20 incorrectly installed into CCS registry
SDSsq43614 BIOS config.importPath gives funky errors if you've spaces between path
SDSsq43624 Missing source file for BIOS 64+ exception handler
SDSsq43625 Broken links in BIOS help file
SDSsq43653 cdb2tcf fails if there is a whitespace in the path
SDSsq43667 vbd needs to bypass L1P when reading data (else corrupt logs on 64x+)
SDSsq43758 The register use appx should doc that the TSR.INT bit is not maintained in BIOS
SDSsq43766 ECM module needs online help
SDSsq43888 DispatchMessageWait is being passed incorrect pointer in VSR module
SDSsq44090 Need to add imcop and ARM to davinci memory map
SDSsq44093 Benchmark for Interrupt latency for Joule/GEM larger than expected
SDSsq44131 config scripts can't use variable named "load"
SDSsq44139 Need to assert when building 64P without -mv64+ option
SDSsq44158 64x+ benchmarks should remove exception handling NMI
SDSsq44221 Graphical config tool fails to open file if install dir contains spaces
SDSsq44351 Need MSGQ_isLocalQueue API
SDSsq44403 Receiving error messages in trace log when using RTDX on DaVinci
SDSsq44427 CACHE_L2 object base address is incorrect for DaVinci
SDSsq44428 BIOS config needs to manage CACHE_L1 objects
SDSsq44431 CLK_reconfig incorrectly sets CLK_htimePerLtime for c64x+ chips
SDSsq44432 MEM_alloc w/ alignment might fail even though a valid block is available
SDSsq44462 device_regs is not defined in Platform.tci file for sim62xx
SDSsq44480 BIOS not working when running 32-bit unchained mode in big endian
SDSsq44490 'bios.enableMemoryHeaps(prog)' should enable default heap
SDSsq44492 Himalaya platforms (.cdb) should hard code CLK freq as 'CPU/6'
SDSsq44503 Incorrect stackseg field description for TSK manager
SDSsq44511 HWI_ATTRS not documented in BIOS API ref guide
SDSsq44516 MSGQ needs more async MQT error codes
SDSsq44520 name for evmDaVinci external memory (DDR) in BIOS 5.20.03 is incorrect
SDSsq44548 CLK for Davinci/Himalaya and HWI_eventMap() doc updates (64x+ only)
SDSsq44549 add examples for Himalaya DSK (dsk6455)
SDSsq44568 MEM_alloc() should get memory at start not end of a free block

Validation Information

Codegen versions used in BIOS 5.21 product validation (as shipped in 3.2 beta2), see kernel release notes for the codegen versions used to build the target content

ISA Compiler in CCS 3.1          Compiler in CCS 3.1 for 67x+

 Compiler in CCS 3.2 beta2

6000 (64P)     cl6x    v6.0.1b2

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_20.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.21.00.04 with directory  bios_5_21_00_04) and the final release will be bios_5_21 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.21.03 with directory bios_5_21_03.  

Point releases where new features such as additional device support are released same as major baselines, ie with patch counter of zero and removed from directory qualifier, ex. 5.21 with directory bios_5_21.  When referring to the release, the term bios "five dot twentyone" generally refers to the baseline bios 5.21 and the patches (ex. 5.21.03) and point releases (ex. 5.22) the comprise the compatible group.



 

 

DSP/BIOS v5.20 (5.20.03) Release Notes

 

Last updated: 07 November 2005

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Fixed In This Release", "Known Issues", and "Validation Info".   

 

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package (updated)
  DSP/BIOS Kernel Benchmarks (updated)
  XDC Tools (Tconf) Package
  DSP/BIOS Platforms
  DSP/BIOS Examples (updated)
  Real Time Data Exchange (RTDX) (updated)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support)
  DSP/BIOS Help Files
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD)
  DSP/BIOS Graphical Configuration Tool (Gconf) (updated)

General Information

DSP/BIOS 5.20.03 is a bug fix update to 5.20.02.   This is a full release and will be installed in <installdir>/bios_5_20_03.

No other changes have been made from 5.20.02.  See the release notes for 5.20.02 below for more information.   

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.20.03

Fixed In This Release

The following bugs have been fixed in this release.  These bugs are listed in the sub-component release notes, but provided here for convenience.

Identifier Headline
SDSsq42743 CLK_reconfig needs CLK_inputClock for omap2430
SDSsq44027 CLK_reconfig has problems on Joule/GEM arch
SDSsq44138 BIOS 5.20.02.28 install dialog reports incorrect destination dir
SDSsq44158 64x+ benchmarks should remove exception handling NMI
SDSsq44164 CLK_countspms and CLK_getprd should relate to htime counts
SDSsq44183 bios.CLK.INPUTCLK can only take whole number values for 2430
SDSsq44207 BIOS SWI can erroneously run on a TSK stack
SDSsq44212 Makefiles Vs Project files has different flag options
SDSsq44319 CLK_gethtime returns higher than expected value, then rolls back
SDSsq44322 HWI dispatcher cache control fields should not be visible on C64P
SDSsq44356 BIOS needs to update interrupt selector to connect RTDX to 11 and 12

 

Validation Information

Codegen versions used in BIOS 5.20.02 product validation (as shipped in CCS 3.1 / 3.2 beta), see kernel release notes for the codegen versions used to build the target content

ISA Compiler in CCS 3.1          Compiler in CCS 3.1 for 67x+

 Compiler in CCS 3.2 beta1

2800 cl2000  v4.1.0    
5400 cl500   v4.1.0    
5500 cl55    v3.2.2    
6000 cl6x    v5.1.0    
6000 (67P)   cl6x    v5.3.0  
6000 (64P)     cl6x    v6.0.1b1

Known Issues

   Installation Directory " " problem -- The configuration update tools (cdb2tcf) that update 4.90 configuration files and .pjt files do not work well when BIOS is installed in a directory with spaces (e.g., "Documents and Settings").  Best work-around is to avoid installing into a directory with spaces.  Another work-around is to run the 'cdb2tcf' utility from the command line.  This is only a problem for the configuration update tools.  All other tools work fine when installed in a directory with spaces.  There are two bugs related to this -- SDSsq43653 and SDSsq44075 -- which will be fixed in a future release.

    64x+ RTA/RTDX problem -- The DSP/BIOS real-time analysis (RTA) plugins are now working but require a workaround when used in CCS 3.2 beta1.  The "RTDX enable channel" API from the RTA plugins does not work in CCS 3.2 beta1.  The workaround is to change RTDX_fromHost$rtdx and RTDX_toHost$rtdx to 0x1010 in a memory window after loading your program and running to main() (i.e., "go main").  This is covered by SDSCM00002244 which will be fixed in a future release of CCS.

    LOG/RTA display problem (SDSsq43667) -- The RTA LOG plugin can display invalid or stale data when the target is halted and the LOG buffer is adjacent to code.  This is due to a problem in the vbd.dll where the code does a read of memory using the CCS/JTAG/emulation memory read APIs.  The problem only occurs if the log buffer is adjacent to a segment of code that has been loaded in the L1P cache.  Since the 64x+ does pre-fetch of code, it is possible for the log data to also reside in the L1P cache.  If this happens, the stale data from L1P will be read instead of the correct data from data memory.  A new CCS API has been created to allow for bypass of L1P when reading data.  vbd.dll will be updated to use this new API in a future release of DSP/BIOS.  A good workaround is to reserve a separate MEM segment for your LOG buffers data and the ".rtdx_data" sections.  Be sure that the base address of this section is not within 5 fetch packets (160 bytes) of any program memory (anchoring this memory at at low address of a given memory block is an easy way to do this).

    RTDX/RTA/L1P problem (SDSsq44403) -- This issue is similar to the "LOG/RTA display problem" noted above but this problem happens in when program is running and the displays are updating in real time.  In this case, you will see garbage data in the LOG, STS or CPU load plugins.  It appears that the RTDX monitor will find data in the L1P memory if the "RTDX_Buffer" is adjacent to code that is in L1P cache.  Workaround for this problem is the same -- create a separate memory section for LOG buffers and RTDX data (.rtdx_data).  Both of these issues are being reviewed and fixes will be found in a future version of DSP/BIOS or CCS.

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_20.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.20.03.31 with directory  bios_5_20_03_31) and the final release will be bios_5_20 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.20.03 with directory bios_5_20_03.  

Point releases where new features such as additional device support are released same as major baselines, ie with patch counter of zero and removed from directory qualifier, ex. 5.21 with directory bios_5_21.    When referring to the release, the term bios "five dot two" generally refers to the baseline bios 5.20 and the patches (ex. 5.20.03) and point releases (ex. 5.21) the comprise the compatible group.

 



 

DSP/BIOS v5.20 (5.20.02) Release Notes

 

Last updated: 29 September 2005

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Fixed In This Release", "Known Issues", and "Validation Info".   

 

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package (updated)
  DSP/BIOS Kernel Benchmarks (updated)
  XDC Tools (Tconf) Package  (updated)
  DSP/BIOS Platforms (updated)
  DSP/BIOS Examples (updated)
  Real Time Data Exchange (RTDX)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support) (updated)
  DSP/BIOS Help Files
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD)
  DSP/BIOS Graphical Configuration Tool (Gconf) (updated)

General Information

DSP/BIOS 5.20.02 is a patch upgrade that adds support for linking BIOS applications with the BIOS code that is included in the on-chip ROM for the C672x (C67x+) devices. Examples have been added for the PADK C6727 board.  These examples are configured to use the BIOS in the on-chip ROM.   See the DSP/BIOS Kernel Release Notes for more information on how to use the code in the ROM.

A number of bug fixes have also been included in this release.  Check the sub-component release notes (highlighted with "(updated)" above) for the specific bug fixes.

No other changes have been made from 5.20.00 or 5.20.01.  See the release notes for 5.20.01 below for more information.   

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

What's New in BIOS 5.20.02

Fixed In This Release

The following bugs have been fixed in this release.  These bugs are listed in the sub-component release notes, but provided here for convenience.

 

Identifier Headline
SDSsq43083 BIOS 5.20 CCS help doesn't show for 'new' modules
SDSsq43317 better handling of cdb backup file in cdb2tcf
SDSsq43324 Bios5.2:Could not locate biosTCI6482.a64Pe for Himalaya in Big End. mode
SDSsq43332 Statically created MBX objects allocate more memory space than needed
SDSsq43364 latency example fails on dsk5510 and teb5561 without -mg option
SDSsq43394 PWRM_init should be called before DEV_init
SDSsq43404 evmDavinci examples should not pass params when using named platfrom
SDSsq43423 Huge Model Dispatcher bug with dispatch table that crosses page boundary
SDSsq43430 DSP/BIOS 5.20 Tutorial topics not found
SDSsq43448 Davinci/Himalaya timers need to use/doc only 32-bits of 64-bit timers
SDSsq43464 TIMER1BASE address is set incorrectly in the BIOS config file
SDSsq43561 BIOS generated linker command file doesn't GROUP stack and systack
SDSsq43602 TSK_getenv inline version has compile errors
SDSsq43665 Joule ITSR register not restored in HWI dispatcher in DSP/BIOS 5.20.0
SDSsq43725 Remove hardcoded x2 factors in 55x CDB files.
SDSsq43733 cdb2tcf does not correct all memory references when 'space' changes
SDSsq43750 CACHE_L2 object not getting destroyed when cache disabled
SDSsq43765 MSGQ STATICPOOL allocator src code should be included in BIOS
SDSsq43844 hidden config fields make removal of MEM objects tough (can do frm .tcf)
SDSsq43846 CLK_stop is missing return statement for 5501/5502 version of BIOS 5.20
SDSsq43876 Add bios install centralized location notes to Setup Guide
SDSsq44008 Makefile,67P is missing from the sabios5.20.02.25
SDSsq44019 re: GBL_initdone not found! DSP/BIOS is not running error window appeari
SDSsq44020 makefile,omap is failing to build omap in linux and solaris
SDSsq44032 remove 'GBL.CHIPTYPE' from common*.tci and hello examples for 6x
SDSsq44034 risky asm/C misc in BIOS's boot.c breaks when update to 6.0.1 tools

Validation Information

Codegen versions used in BIOS 5.20.02 product validation (as shipped in CCS 3.1 / 3.2 beta), see kernel release notes for the codegen versions used to build the target content

ISA Compiler in CCS 3.1          Compiler in CCS 3.1 for 67x+

 Compiler in CCS 3.2 beta

2800 cl2000  v4.1.0    
5400 cl500   v4.1.0    
5500 cl55    v3.2.2    
6000 cl6x    v5.1.0    
6000 (67P)   cl6x    v5.3.0  
6000 (64P)     cl6x    v6.0.1b1

Known Issues

   Installation Directory " " problem -- The configuration update tools (cdb2tcf) that update 4.90 configuration files and .pjt files do not work well when BIOS is installed in a directory with spaces (e.g., "Documents and Settings").  Best work-around is to avoid installing into a directory with spaces.  Another work-around is to run the 'cdb2tcf' utility from the command line.  This is only a problem for the configuration update tools.  All other tools work fine when installed in a directory with spaces.  There are two bugs related to this -- SDSsq43653 and SDSsq44075 -- which will be fixed in a future release.

    64x+ RTA/RTDX problem -- The DSP/BIOS real-time analysis plugins do not work for this release due to a possible problem in the RTDX layer for 64x+.  This problem is specific to the 64x+.  It was not known at release time if the problem is one of the BIOS 5.20.02 components or if the problem is in one of the CCS 3.2 beta1 components or emulation driver.   Since the problem might not be in a BIOS component, this might be fixed in a newer release of CCS 3.2 or the emulation driver.  If the problem is in one of the BIOS components, a new point release will be made.  Investigation is on-going.

    Additional Issues -- See known issues in sub-component release notes and 5.20.01 release notes below.

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_20.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.20.00.15 with directory  bios_5_20_00_15) and the final release will be bios_5_20 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.20.01 with directory bios_5_20_01.  

Point releases where new features such as additional device support are released same as major baselines, ie with patch counter of zero and removed from directory qualifier, ex. 5.21 with directory bios_5_21.    When referring to the release, the term bios "five dot two" generally refers to the baseline bios 5.20 and the patches (ex. 5.20.01) and point releases (ex. 5.21) the comprise the compatible group.

 



 

 

DSP/BIOS v5.20 (5.20.01) Release Notes

 

Last updated: 16 August 2005 (updated release notes)

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Fixed In This Release", "Known Issues", and "Validation Info".   

 

Release Notes for each separately versioned sub-component package:

  DSP/BIOS Kernel Package
  DSP/BIOS Kernel Benchmarks
  XDC Tools (Tconf) Package 
  DSP/BIOS Platforms
  DSP/BIOS Examples
  Real Time Data Exchange (RTDX)
  Power Scaling Library (PSL)

Sub-components applicable to Windows installations used with Code Composer Studio:

  OsAware (Kernel Object View support)
  DSP/BIOS Help Files
  DSP/BIOS Build Tools Interface (BTI) for CCS
  Real Time Analysis Infrastructure (VBD)
  DSP/BIOS Graphical Configuration Tool (Gconf)

General Information

DSP/BIOS 5.20.01 is a patch upgrade that is intended to replace BIOS 5.20 as an update to release notes and a rebuild of the examples package - no change to the other content in BIOS 5.20

DSP/BIOS 5.20 provides a rollup of 5.1x patches and point releases and provides bug fixes and customer driven enhancements.   Device support is listed below.   DSP/BIOS 5.20 is available for Windows XP, Linux Red Hat and Solaris host development environments.    

It is strongly recommended to follow the instructions in the DSP/BIOS Setup Guide, also available from the documentation index for information on updating from previous BIOS releases and instructions on how to use the BIOS Selector in the Component Manager of Code Composer Studio.

 

What's New in BIOS 5.20


 

 

Device Support

     
  Devices Supported* Runtime model
 

*BIOS Configuration DeviceName listed

 
     
28xx Devices    
  F2801
F2806
F2808
F2810
F2811
F2812
 
Large model
     
54xx Devices    
 
5402
5402A
5409A
5416
5470
5471
5405
 
Near and Far model supported
     
55xx Devices    
  5501
5502
5503
5507
5509A
DA255
5510
5510A
5561

 

Large model on Laijin 2.x core devices

Note: 55xx small model support has been dropped starting with BIOS 5.10

     
Hetero Devices (OMAP 55xx DSP)    
  5903
5905

5910
5912

5948
5946
5944


1510
1610
1710
2420
 

TNETV1050
TNETV1055

 

Large model for 55xx DSP side of Heterogeneous multi processors (OMAP: ARM + 55xx DSP, Titan: MIPS + 55xx DSP)

Large and Huge model for 55xx DSP on Laijin 2.x/3.x, such as OMAP1710, OMAP2420

Note: 55xx small model support has been dropped starting with BIOS 5.10

     
62xx Devices    
  Not Supported: C6201
6202
6203
6204
6205
6211

 

Big and Little Endian
     
67xx Devices    
6701
6711
6711 - 250
6712
6713
6713 - 300
 

 

Big and Little Endian
     
67Pxx Devices    
  DA705
DA707
DA710
6722
6726
6727

*Note:  If you wish to use BIOS in the on-chip ROM use v5.10.02 or newer compatible release.   BIOS 5.20 can be used RAM based.

 

Big and Little Endian
     
64xx Devices    
  6410
6411
6412
6413
6414
6415
6416
6418
DRI300
DM640
DM641
DM642

 

Big and Little Endian
     
64Pxx Devices    
  TCI6482
6455

 

Big and Little Endian
     
IAG Devices    
  DM270
DM310
DM320

DA300*
DA295*

*Note: If you wish to use BIOS in the on-chip ROM (DA300 and DA295) use v5.10.02 or newer compatible 5.1x release.   BIOS 5.20 can be used RAM based.

 

 


Fixed In This Release

Each DSP/BIOS sub-component provides release notes detailing bug fixes, installer bug fixes are listed here:  

 

BIOS Installer:    
  SDSsq43186 Windows DSP/BIOS Installer Destination Browser is Confusing
     
CCS Integration:    
  SDSsq42791 CCS does not allow the cdb file type (File->Open) for opening CDB files read-only with BIOS 5.20 selected.   
     

 


Known Issues

See below for product level errata (install, etc.) and issues found in final validation and not covered in sub-component release notes:

 

BIOS Installer:    
  SDSsq43196 Important Note for BIOS 5.20 Early Adopter (EA1 / EA2) users.   You must un-install BIOS 5.20 EA1 / EA2 prior to installing BIOS 5.20.   Uninstalling the EA release after installing the release of BIOS 5.20 will unregister Gconf.exe - the fix for this is to re-install BIOS 5.20.  

Gconf is not unregistered by the uninstaller in the BIOS 5.20 release version.

     
  SDSsq39970 Uninstaller does not remove/delete base dir bios_5_20 while uninstalling
     
  SDSsq39813 Uninstall removes BIOS Selector registry keys for multiple 5.10 installs
     
  SDSsq37229 DSP/BIOS installer gives vague message when out of space
     
  SDSsq43117 Linux install does not fail if disk quota exceeded
     
  SDSsq38132 DSP/BIOS installer (Installshield) hangs on some versions of Red Hat Enterprise edition.   There is a workaround for this problem posted on an Installshield discussion site, excerpted below.

http://community.installshield.com/showthread.php?s=a54b7cd8d1dd0149e214f01cbf617406&threadid=134592

A workaround for the Installshield hang:

1. Run the following Bourne shell commands on the Linux machine:

cd /tmp
mkdir bin.$$
cd bin.$$
cat > mount <<EOF
#! /bin/sh
exec /bin/true
EOF
chmod 755 mount
export PATH=`pwd`:$PATH


2. Run your BIOS 5.10 installation.

3. When the installer is finished running, run the following command.

rm -r /tmp/bin.$$

     
CCS Integration:    
     
  SDSsq42832 BIOS 5.20 tutorial is not available in CCS 3.1 Help->Tutorial menu.   

To access the BIOS 5.20 Tutorial, make sure BIOS 5.20 is selected in Component Manager (BIOS Selector), Open in CCS the Help->Contents menu, then expand the DSP/BIOS 5.20 topic to find the tutorial as a subtopic.

     
  SDSsq43335 Install order issue.   Installing CCS 3.1 after installing BIOS 5.20 requires the update of the TConfCmdObject.ocx plug-in to get proper operation of BIOS 5.20 in CCS 3.1.

A non-visible CCS plug-in known as the TconfCmdObject is installed into the available CCS 3.1 installations when BIOS 5.20 is installed.    Since this update is done as part of the BIOS installation process, the user must manually update CCS if CCS is installed after BIOS.    This plug-in implements the automatic project update from CDB to TCF and is responsible for providing the file interface for Tconf path information to Gconf.

In the case where BIOS is installed before CCS 3.1, this file will not be updated and the user must run the update utility located in <install_dir>\bios_5_20\packages\ti\bios\bti\bin\UpdateTconfCmdObject.exe.     CCS 3.1 users can verify the copy was done correctly by checking the file in CCStudio_v3.1\bin\utilities\tconf\TconfCmdObject.ocx to insure it is the same version as that supplied by BIOS 5.20 in the directory containing the update utility.

     
  SDS43084 The BIOS Selector allows BIOS versions to be chosen on a per ISA basis, the CCS project contains a parameter, CPUFamily, that is used to determine the ISA of the project that is opened to select the correct BIOS.   If users have copied the project file from a different ISA, then the proper BIOS version will not be selected.  

The workaround is to insure the CPUFamily parameter in the project file matches the ISA intended.     Some BIOS 4.90 projects distributed in CCS 3.1, specifically in the sim64xx folder have the CPUFamily set incorrectly to c62xx.

     
Kernel:    
  Info The kernel is not 'binary' compatible with that shipped in BIOS 5.10 due to some bug fixes that changed a data structure - users will need to rebuild applications and dependent libraries.
     
  Info DSP/BIOS Task 'Stack Size'.   The HWI interrupt dispatchers (for 55x and 6x) were optimized for improved performance in this release.

One consequence of this optimization is that all task stacks must be large enough to accommodate one interrupt context (compiler save-on-call registers) along with task function requirements.   This same constraint was true in prior releases of the product (BIOS 4.90 and 5.x), but there was an implementation artifact, where the highest priority task (or tasks if there are more than one task at the highest priority) did not have to accommodate these registers. 

When updating to this version of the kernel, be sure that your highest priority task(s) (those that share same exact highest priority level) have stacks large enough to handle these save-on-call registers.
 

     
  Info MEM or RTS functions may cause SYS_abort() (SDSsq37410)

The DSP/BIOS Kernel uses internal lock/unlock function to protect the MEM heaps and certain runtime support library (RTS) functions from reentrancy. These functions use LCK_pend/post() but these APIs cannot be safely called from HWI or SWI context.

There have been several customer problems where customers were unknowingly calling RTS and/or MEM from incorrect context which would cause intermittent/infrequent system crashes.

We have therefore updated the internal lock function to verify calling context (with TSK_isTSK()) before calling LCK_pend().

If the calling context is not a TSK, this API will call SYS_abort() which will typically halt the processor with interrupts disabled.

Customers upgrading to 5.20 may have to modify their code if they were previously calling MEM or RTS from incorrect context (to avoid call to SYS_abort()).
 

     
  Info 55xx small model support has been dropped since BIOS 5.10.   BIOS 4.90 users will need to change to large model when updating.
     
  SDSsq43324 Linker error: could not locate biosTCI6482.a64Pe for C6455 / TCI6482 in Big Endian.

The big endian timer library, biosTCI6482.a64Pe, was inadvertently not included in the BIOS 5.20 release - this will result in a link failure when building big endian for TCI6482 devices.

     
     
Configuration    
  SDSsq42784

Commandline users of Tconf must explicitly add the path to the bios packages directory, for example:

-Dconfig.importPath=c:\bios_5_20\packages   

In BIOS 5.10 this path was provided by tconflocal.tci and since this use of tconflocal.tci is being deprecated it h as been removed in BIOS 5.20.   GConf and CCS both supply the default path to the BIOS packages directory for CCS users.

     
  SDSsq39373
Rhino TCF Script Debugger:  A certain class of syntax errors in tcf files can cause the Rhino debugger to exit just after starting up.


A tcf file with first-pass parsing errors causes the rhino debugger to exit with no chance to break or view the cause of the error.  This is due to a debugger startup issue where the syntax error is found early in the sequence of starting the debugger and a breakpoint is not yet set.

 

The following is a simple test.tcf file to produce the error:

print("In test.tcf");
I made a mistake
print('got here');


The recommendation is to debug this class of error by looking at the line number error output from launching Tconf on the script - in CCS, this error can be double clicked and the text editor will start and take you to the line number (provided Gconf is not already open on the tcf file).   For example, launching Tconf on a tcf script with the error will result in the following:
 
js: "c:\test.tcf", line 2: missing ; before statement
js: I made a mistake
js: .....^
js: "c:\test.tcf", line 1: Compilation produced 1 syntax errors.

 

     
Examples:    
  SDSsq43328 Sim55xx and DSK5510 examples have pjt files which use are set to use mnemonic assembly mode, the other 55xx examples are set to use algebraic with the -mg flag.   The examples when run produce incorrect results in some cases, for instance the latency example.  

The workaround is to set the -mg (algebraic) flag for the BIOS generated assembly file.

     
     
RTA / RTDX:    
  SDSsq42433 Problems with RTA / RTDX in CCS 3.1 when using XDS-560 and 6713 have been found.   The workaround is to specify the JTAG clock frequency rather than have it auto-configured. 

Procedure:  Open CC Setup, load the 6713 XDS-560 config file, right->click properties, then choose "Connection Properties" tab.    Change TCLK from "Automatic" to "User Defined", this creates a new property called "JTAG Clock Rate", change this from default of '1' to '30'.

     
  SDSsq36236, SDSsq37018, SDSsq37019 When using the PDM you cannot get RTA in any CCS windows if you select the "Global Breakpoints" from the PDM options menu.
 
     
     
Documentation / Help:    
  SDSsq43178 DSP/BIOS 5.20  Help sometimes does not appear when selecting Help->Contents in CCS.     The workaround is:
  1. Assuming BIOS 5.20 is selected in Component Manager (CM), Start CM and select BIOS 4.90 where 5.20 was previously selected.  Save and exit CCS and CM.
  2. Start CM again, select BIOS 5.20 in the ISA of choice, Save and Exit CM.
  3. Start CCS, there should not be a "New Components Detected" dialog box.
  4. Select Help->Contents, DSP/BIOS 5.20 topic should be there.

 

     
  Info The new BIOS tutorial is available in CCS 3.1 / 3.2 by selecting Help->Contents and then expanding the DSP/BIOS 5.20 topic.    A link to the tutorial has also been included in the documentation index.
     
  SDSsq43363 C28x Tutorials Steps6: building the project , make sure to specify (-ml) option for compiler as only large model is supported for 28xx devices
     
  SDSsq43362 In the tutorial, section on scheduling multiple tasks step6: building the project-> 4th point refers incorrectly to clk.c , should be mutex.c for this section.
     
     

 

 

 


Validation Info

BIOS 5.20 is validated against the following versions of Code Composer Studio (CCS).   

 

The release was tested for configuration and build on the following host operating systems

Codegen version dependency:

    Codegen versions used in BIOS 5.20 product validation (as shipped in CCS 3.1 / 3.2 EA5), see kernel release notes for the codegen versions used to build the target content

ISA Compiler in CCS 3.1

 Compiler in CCS 3.2 EA5

2800 cl2000  v4.1.0  
5400 cl500   v4.1.0  
5500 cl55    v3.2.2  
6000 cl6x    v5.1.0  
6000 (64P)   cl6x    v6.0.0

 

Note on BIOS versioning:    The BIOS product version follows a version format, M.mm.pp.b , where M is single digit Major version, mm is 2 digit minor version, pp is 2 digit patch, and b is an unrestricted set of digits used as incrementing build counter. 

To support multiple installations of different bios versions, the product version is encoded in the top level directory, ex. bios_5_20.   Interim deliveries of major baseline bios releases, such as a beta or early adopter (EA), will have a full qualified version (ex. 5.20.00.15 with directory  bios_5_20_00_15) and the final release will be bios_5_20 following the convention of stripping the patch and build counter for final release.  

Subsequent releases of patch upgrades will be identified by the patch number, ex. bios 5.20.01 with directory bios_5_20_01.  

Point releases where new features such as additional device support are released same as major baselines, ie with patch counter of zero and removed from directory qualifier, ex. 5.21 with directory bios_5_21.    When referring to the release, the term bios "five dot two" generally refers to the baseline bios 5.20 and the patches (ex. 5.20.01) and point releases (ex. 5.21) the comprise the compatible group.

 

 



 

 

DSP/BIOS v5.10.01 Release Notes

 

Last updated: 20 January 2005

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Fixed In This Release", "Known Issues", and "Validation Info".     

 

Release Notes for each separately versioned sub-component packages.:

DSP/BIOS Kernel Package (updated)
XDC Tools Package  (updated see below for info)
DSP/BIOS Platforms
DSP/BIOS Examples
Real Time Analysis Infrastructure (VBD)
Real Time Data Exchange (RTDX)
Power Scaling Library (PSL)

BIOS Selector components (applicable to Code Composer Studio on Windows):

OsAware (Kernel Object View support)
DSP/BIOS Help Files
DSP/BIOS Build Tools Interface (BTI) for CCS
 



 

 General Information

DSP/BIOS 5.10.01 is an update for BIOS 5.10.00 that fixes a problem found by OMAP Software when building DSP Bridge based apps using v2.77 55xx codegen, see kernel package release notes for details.    

 

 

What's New

 

 

 


Fixed In This Release

Each DSP/BIOS sub-component provides release notes detailing bug fixes.   Except:



 

 


Known Issues

See below for product level errata (install, etc.) and issues found in final validation and not covered in sub-component release notes:

Same as BIOS 5.10.00 (see below)

     
     
     

 

 

 


Validation Info

BIOS 5.10.01 is validated against the following versions of Code Composer Studio (CCS).   

 

The release was tested for configuration and build on the following host operating systems

Codegen version dependency:

    Same as 5.10.00

 

 



 

 

DSP/BIOS v5.10.00 Release Notes

 

Last updated: 29 November 2004

The DSP/BIOS distribution is composed of sub-component packages each containing specific release notes.   This top level release note covers general product level issues related to installation and getting started and is divided into four sections, "General Info", "Fixed In This Release", "Known Issues", and "Validation Info".     

 

Release Notes for each separately versioned sub-component package:

DSP/BIOS Kernel Package
XDC Tools (Tconf) Package
DSP/BIOS Platforms
DSP/BIOS Examples
Real Time Analysis Infrastructure (VBD)
Real Time Data Exchange (RTDX)
Power Scaling Library (PSL)

DSP/BIOS Kernel Benchmarks

BIOS Selector components (applicable to Code Composer Studio on Windows):

OsAware (Kernel Object View support)
DSP/BIOS Help Files
DSP/BIOS Build Tools Interface (BTI) for CCS
 



 

 General Information

DSP/BIOS 5.10.00 brings new features for messaging and low power development, modifications to allow ROM'ing BIOS with options for updates and rolls up device and feature support released in BIOS 5.01, 5.02, 5.03 and 5.04.

Reading the Getting Started Guide is highly recommended as this gives necessary info for working with supported CCS versions and steps necessary for upgrading projects especially in updating to the new BIOS config (Tconf) and for the removal static CSL configuration.

 

What's New

 

 

What's Removed

 


Fixed In This Release

Each DSP/BIOS sub-component provides release notes detailing bug fixes.
 



 

 


Known Issues

See below for product level errata (install, etc.) and issues found in final validation and not covered in sub-component release notes:

BIOS 5.10 Install    
  SDSsq38132 BIOS 5.10 installer (Installshield) hangs on some versions of Red Hat Enterprise edition.   There is a workaround for this problem posted on an Installshield discussion site, excerpted below.

http://community.installshield.com/showthread.php?s=a54b7cd8d1dd0149e214f01cbf617406&threadid=134592

A workaround for the Installshield hang:

1. Run the following Bourne shell commands on the Linux machine:

cd /tmp
mkdir bin.$$
cd bin.$$
cat > mount <<EOF
#! /bin/sh
exec /bin/true
EOF
chmod 755 mount
export PATH=`pwd`:$PATH


2. Run your BIOS 5.10 installation.

3. When the installer is finished running, run the following command.

rm -r /tmp/bin.$$

     
  SDSsq39813 Uninstall removes entry in "Add/Remove Programs" and BIOS Selector registry keys for multiple BIOS 5.10 installs (Windows only).     The workaround is to re-install BIOS 5.10 to repopulate the registry information.
     
     
BIOS Selector    
  SDSsq38524 CCS assumes BIOS generated files are the same name as TCF file name
     
  SDSsq38249 BIOS, TConf and BTI help file support not switch able in BIOS Socket / Selector in CCS 2.4
     
     
Configuration (XDC Tools)    
  SDSsq39828 cdb2tcf must enable heap in a segment before assigning it to MEM fields.

The conversion tool cdb2tcf converts configurations from CDB files to TCF scripts that should be executable without any changes.  However, in certain cases the order of instructions in generated tcf scripts is incorrect.  In this case, script that enables heap in a memory segment happens after the memory segment assignment.    The heap needed to be enabled ahead of the assignment, i.e., the script generated by the cdb2tcf utility is not in the correct order and the user will have to edit the generated tcf script to fix the problem.

Error messages that Tconf prints in such situations usually report that there was a write attempt into a read-only field or that there a value is an illegal value for a field.  As stated above, users who encounter this issue should try to reorder instructions until Tconf executes the script successfully and creates a new configuration.   A useful diagnostic is to invoke the Tconf script debugger by adding '-g' to the TConf command line (ex.  tconf -g my.tcf).

 

     
  SDSsq39270 4.90 Gconf Generates Error Dialog for new device cdb file from BIOS 5.10

Workaround is to click OK through the two dialog boxes.

Tconf is used for configuration in BIOS 5.10.    The Gconf supplied in CCS with BIOS 4.90 can be used to view the generated configuration but not to edit the configuration.   For devices not present in BIOS 4.90, when a user tries to view the configuration for the new chip (such as da700.cdb), Gconf is going to compare the current cdb version with that in the base seed.   The base seeds found by Gconf will be those from BIOS 4.90 not BIOS 5.10 since Gconf only knows the BIOS 4.90 search path.   Since da700 was not present in BIOS 4.90, Gconf will generate the error message "Error retrieving version in file da700.cdb: fail to open file".    This is a harmless error since Gconf is being used for viewing not editing - the user should click OK and then OK again to acknowledge the read-only dialog.

 

  SDSsq39986 Tconf / BIOS configuration should generate warning for huge model when RTDX is configured.

The workaround is to make sure that RTDX is disabled and RTA is used in stop mode.

Huge model support has been added in Bios 5.10, but is not yet available in RTDX.   The h3omap1710 and h4omap2420 platforms can be configured and built using huge model for stop mode RTA.  

By default RTDX is enabled when building examples for Bios 5.10.   If the user adds the compiler options and changes the common.tci file in the examples to support huge model and don't comment out the line where RTDX is being enabled they will get a build failure resulting from a cryptic linker command message.   This is a result of the large model RTDX library being linked in (resulting from an error in the huge model base configuration).   This gives and error that incompatible targets is trying to be linked.

     
     
Kernel    
  SDSsq39951 BIOS Timer Clock Rate for DA700 should be 1/4 of SYS_CLK1.  

The workaround is to set the period to 1/2 of the desired value in the BIOS configuration to achieve the correct timing (BIOS is off by a factor of 2).

BIOS uses Timer0 as BIOS timer in DA700. In BIOS configuration, the Timer0 clock rate is set to 1/2 CPU Rate.  In the DA700 device family, the timer clock source should be SYS_CLK2, which is 1/2 SYS_CLK1.  But since BIOS uses Up Counter0 as bypass counter to Free Running Counter0 and the minimum Up Counter period is 2, the actual clock rate for Free Running Counter0 is 1/4 SYS_CLK1.  Consequently, BIOS should configure Timer clock rate as 1/4 of CPU Rate.

     
  SDSsq39074 Duplicate types defined for BIOS 5.10 and CSL 2.x

The std.h file provided with DSP/BIOS 5.10 has some duplicate type definitions with the 2.x CSL types (csl_stdinc.h for 54x and 6x, csl_std.h for 55x).   Source files that include both of these files will yield warnings about redefining same type.

Workaround is to use the -pds303 compiler option to suppress this warning.

     
  SDSsq33561 CLK manager in DM642 cdb should also support timer2

Workaround: Users can use timer2, however an extra step in configuration is required.  First set "Timer 2" as a Hardware Interrupt Vector source before selecting "Timer 2" for the BIOS CLK for c64xx devices.

As an example, if the user wanted to drive the BIOS CLK with Timer2 and use Hardware Interrupt 13 for Timer2 then in the textual configuration script, the user must do the following in the order below:


bios.HWI_INT13.interruptSource = prog.get("Timer 2");
bios.CLK.TIMERSELECT = "Timer 2";
 

     
     
RTA Infrastructure    
  SDSsq39707 Can't run RTA by just loading symbols in CCS 2.4 / 3.0.   

This problem does not occur in CCS 2.21, so a workaround is to use CCS 2.21.    Note: this problem happens in CCS 2.4 and 3.0 using the integrated BIOS 4.90 as well as the updated independently released 5.10.  

Details:  when only loading symbols with the Message Log window open gives error: "Not a BIOS/SPOX program" if using pre-BIOS 5.10 RTA and "Bad COF file or invalid COF path" if using BIOS 5.10 RTA.  Also, if you load symbols and then bring up the message log it is not getting initialized correctly (you will not see any log names in the drop down list and there will still be a message in the Message Log window that says you need to load a program.

 

     
  SDSsq39380 Subsequent reload and run of c6x program fails in CCS 3.0

Subsequent reload and run of c6x program, such as the tsk example, fails in CCS 3.0.    While executing a SWI and TSK examples on DM642 it throws an error:

 “Error: Error 0x0000000C/-2044 Error during: Register, Break
Point, No breakpoint at 0x00011DE0 Sequence ID: 16 Error Code: -2044
Error Class: 0x0000000C
Trouble Halting Target CPU: Error 0x0000000C/-2044 Error during:
Register, Break Point, No breakpoint at 0x00011DE0 Sequence ID: 16
Error Code: -2044 Error Class: 0x0000000C” .


This is an intermittent RTDX issue. To workaround, close and restart Code Composer Studio.
 

     
     
     
     
     
     
     

 

 

 


Validation Info

BIOS 5.10.00 is validated against the following versions of Code Composer Studio (CCS).    The dependent components XDAIS and CSL used for sanity tests are supplied in the CCS used for validation.

 

The release was tested for configuration and build on the following host operating systems

Codegen version dependency:

Note:  kernel release notes lists this table, but has an error on 54xx compiler version (should show 3.83).

Runtime model suffix

Description

Codegen version

for kernel build

Codegen options

Codegen version

for examples and validation

28

28xx small model

N/A

 

N/A

28L

28xx large model

N/A

 

N/A

54

54xx near model

3.83

-c -o2

3.83

54f

54xx far model

3.83

-c -o2 –mf –v548

3.83

55

55xx small model

N/A

 

N/A

55L

55xx large model

2.77

-ml –o2

2.77

55H

55xx huge model

v3.2.0B3

-c -o2

--memory_model=huge

-vcore:3

v3.2.0B3

62

62xx little endian

5.0.0

-c -o2 -ml0 –mi10

5.0.0

62e

62xx big endian

5.0.0

-ml0 –mi10 –o2 -me

5.0.0

67

67xx little endian

5.0.0

-c -o2 -ml0 -mi10 -mv6700

5.0.0

67e

67xx big endian

5.0.0

-c -o2 -ml0 -mi10 -mv6700 -me

5.0.0

67P

67Pxx little endian

5.2.0B4

-c -o2 -ml0 -mi10 -mv67p

5.2.0B4

67Pe

67Pxx big endian

5.2.0B4

-c -o2 -ml0 -mi10 -mv67p   -me

5.2.0B4

64

64xx little endian

5.0.0

-c -o2 -ml0 -mi10 -mv6400

5.0.0

64e

64xx big endian

5.0.0

-c -o2 -ml0 -mi10 -mv6400 –me

5.0.0

64P

64Pxx little endian

5.2.0B4

-c -o2 -ml0 -mi10 -mv64p

5.2.0B4

64Pe

64Pxx big endian

5.2.0B4

-c -o2 -ml0 -mi10 -mv64p   -me

5.2.0B4

 

 

 

 

 

 

Device validation was performed on the following platforms;

28xx Devices    
  No 28xx devices in this release.  
     
54xx Devices    
  Not supported: C5401
C5402
C5402A
C5409A
C5416
C5470
C5471
 
     
55xx Devices    
  C5501
C5502
C5503
C5507
C5509A
DA255
C5510
C5510A
C5561
 
     
OMAP Devices (55xx DSP)    
  OMAP 5903
OMAP 5905
OMAP 5910
OMAP 5912

OMAP 5948
OMAP 5946
OMAP 5944


OMAP 1510
OMAP 1610
OMAP 1710
OMAP 2420
 

 
     
62xx Devices    
  Not Supported: C6201
C6202
C6203
C6204
C6205
C6211
 
     
67xx Devices    
  C6701
C6711
C6711 - 250
C6712
C6713
C6713 - 300
DA7xx
 
     
64xx Devices    
  C6410
C6411
C6412
C6413
C6414
C6415
C6416
C6418
DRI300
DM640
DM641
DM642
 
     
     
IAG Devices    
 
DM270
DM310
DM320

DA300
DA295