| ID |
Summary |
State |
Reported In Release |
Target Release |
Workaround |
Release Notes |
| CODEGEN-4638 |
When shift counts are higher than 32, compiler sometimes optimizes to an incorrect shift count |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
Turn off optimization by using optimization level off.
Otherwise, avoid a left-shift by a constant as an operand of the listed operations. However, compiler optimizations could interfere with this. Try keeping the shift count in a global variable instead of as a literal, or computing the shift separately into a variable (a global or volatile local) and doing the |, +, etc, on the variable. |
Left shifts by 32 or more, as an operand of +, -, &, |, or ^, (eg, ((X<<56) | (Y<<48))) may produce incorrect results. |
| CODEGEN-4622 |
Builtin test __has_builtin incorrectly claims to support many __builtin functions |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
Do not use __has_builtin until it is fixed. |
MCU release 18.1.x.LTS added the __has_builtin feature to detect whether or not a particular builtin function was supported. However, this feature test mistakenly returned true for a great number of builtins that the TI compiler does not support. |
| CODEGEN-4605 |
Incompatible redeclaration error with -o4 when using anonymous unions |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
Do not use anonymous structs or unions; give all struct members a name, even if it is never used. |
Anonymous structs and unions are a GCC extension. They are members of a parent structure and have no names. You access the elements inside them as if they were direct members of the parent class. If you have an anonymous struct or union inside a union and you use -O4 optimization, you may get the mistaken error "symbol so-and-so redeclared with incompatible type" at link time. This bug can only happen in COFF mode.
Essentially the same bug was previously fixed for EABI and was known as CODEGEN-1191. |
| CODEGEN-4581 |
Using the C interlister with C++14 features may generate error |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
Do not use the -s source interlisting option |
When using the -s C source interlisting option, the compiler may emit a bogus assembly directive for functions which do not have a body in the source code (e.g. certain implicit constructors). The assembler will emit an error when encountering this directive. |
| CODEGEN-4576 |
hex --ascii option truncates address to 16 bits |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
Use the hex converter from an earlier release |
When generating an "ASCII" format hex file, the hex converter would mistakenly truncate addresses to the lower 16 bits. |
| CODEGEN-4426 |
Compiler crashes when building TI-RTOS in SIMPLELINK-MSP432-SDK 1.60.00.12 version of the SDK |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.1.LTS |
|
The failure was found when building the gpiointerrupt_MSP_EXP432P401R_tirtos_ccs project from version 1.60.00.12 of the Simplelink MSP432 SDK. However, the failure occurs when building TI-RTOS kernel so most likely affects all examples. The failure has only been reproduced on OSX, but it could be encountered on any OS. The failure is a crash and will result in an error message like:
INTERNAL ERROR: armacpia experienced a segmentation fault
while processing function (unknown or file scope) file (unknown) line 0
This is caused by a defect in the TI EABI C/C++ Parser.
>> Compilation failure
TI Customer Support may be able to suggest a workaround to avoid this.
Upgrading to the newest version of the compiler may fix this problem. |
| CODEGEN-4419 |
Compiler erroneously speculates indexed load from the stack |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
Modify the source code of the offending function to make local variables "volatile." There's no obvious way to pre-determine that a function will suffer from this bug; you just have to wait for the bug to happen, look at the line number of the offending instruction (which will always be a load with indexed addressing with base register SP), and go to the function at that line number. Make every local variable in that function "volatile." If it's a C++ function, you may need to make the function "volatile." |
The compiler moves instructions from one block to another to increase parallelism. Usually this is done by predicating (adding a condition to) every instruction that is moved above a branch. However, in some cases, the compiler will "speculate" the instruction, which means removing the condition entirely. This is done when the instruction's side-effects are judged to be safe, such as load of a local variable. In the case that the instruction's condition would have been false, this load will be useless, but at least it will be safe, because the stack pointer (SP) is at a legal location, and there won't be a memory fault. However, when a local variable's value is read with an indexed expression, the index register is not necessarily speculated exactly when the load is, so the index register may have a garbage value. In this test case, the load was speculated, but the index register definition wasn't, so in the false branch, the computed address was garbage, and we would read a random memory address, causing a memory fault. (Even though SP was perfectly valid, the index register was garbage, so SP+index might point anywhere in memory.) |
| CODEGEN-4407 |
Not using const causes unexpected build error when calling std::sort |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
Remove unnecessary const from helper in s__algo.c |
|
| CODEGEN-4339 |
div() and ldiv() return incorrect result when built with -o4 option |
Fixed |
|
ARM_18.1.0.LTS |
|
|
| CODEGEN-4280 |
Using ULP advisor with C++ templates may cause the compiler to crash |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
|
The compiler may crash when using ULP advisor on C++ code that contains templates |
| CODEGEN-4251 |
ECC section names are randomly assigned |
Fixed |
|
ARM_18.1.0.LTS |
|
This happens in 16.9.X.LTS because the ECC initialization code iterates over an unsorted list. This list's order happens to be non-deterministic. The ECC code was refactored significantly before the 17.3 branch, and now uses a set, which is always ordered. Thus, the problem will not occur in 17.3.0.STS or any release thereafter. We do not plan to address this for the 16.9.X.LTS branch. |
| CODEGEN-4182 |
Should ignore option --pending_instantiations when compiling C files |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
If the user wishes to use the option --pending_instantiations, they must add this option individually to each C++ file. |
The compiler option --pending_instantiations only makes any sense when used with C++ code. It cannot have any effect on C code. Indeed, when passed as an option to a compilation of C code, the compiler will stop and emit an error, "pending instantiations option can be used only when compiling C++"
This is troublesome when trying to compile a mixture of C and C++ files in CCS. If the user wishes to use the option --pending_instantiations, they cannot just add this option to the global compiler options list; they must add this option individually to each C++ file. |
| CODEGEN-4113 |
Assembler computes wrong result for expression 0x232800 % 0x10000 |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
In some instances, as in the original test case, the AND operator can be used instead, but that is not a general workaround. |
The modulo operator in the TI assembler, for releases made in mid-to-late 2016 and all of 2017, is unreliable. In some cases it will produce an incorrect answer. |
| CODEGEN-4078 |
LInker takes over 5 minutes to finish |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
None. If the linker command file wants to be that specific about memory ranges, then the work has to be done, and the option to disable the work has its own bug. |
Linking may take excessively long when the linker command file specifically places a lot of variables at specific addresses, especially for C2000. The original report was placing more than 300 variables. The --no_placement_optimization option is not a workaround because it causes a linker crash. Both problems are fixed together. |
| CODEGEN-3955 |
libc++ has incorrect implementation of pointer_safety |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.0.LTS |
|
The implementation of std::pointer_safety is a struct, rather than as an enum_class, as required by the C++ standard. |
| CODEGEN-3931 |
Compiler crashes while handling 0 length array in zero sized struct |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
None |
The compiler crashes while parsing a struct or class with zero-sized members in C++ mode. |
| CODEGEN-3880 |
Compiler generates invalid instruction with VFP registers |
Fixed |
|
ARM_18.1.0.LTS |
No practical workaround |
When using --float_support, it is sometimes possible for VFP registers to show up in regshift operands. If you do not get an error from the assembler, you are not suffering from this bug. |
| CODEGEN-3858 |
OFD gets DIE attribute offset wrong when using --dwarf_display=none,dinfo |
Fixed |
|
ARM_18.1.0.LTS |
If you use --dwarf_display=none,dinfo, use --dwarf_display=none,dinfo,types instead |
You can use OFD to display the DWARF debugging information in your object files by using the option '--dwarf' (or -g). You can narrow the categories of DWARF information displayed by using the '--dwarf_display' option. If you use the option --dwarf_display=none,dinfo you will see the DWARF DIE objects in the .dwarf_info section, but you will not see any DW_AT_type attributes unless you also use the "types" flag. This is not a bug. However, when OFD skips a DW_AT_type attribute, it displays the offset of the skipped DW_AT_type for the next attribute instead of the next attribute's correct offset. |
| CODEGEN-3801 |
Linker crashes with INTERNAL ERROR (unhandled exception) |
Fixed |
|
ARM_18.1.0.LTS |
|
The linker experiences a segmentation fault when there is a reference from a debug section to a symbol without a section (for example, an absolute symbol). |
| CODEGEN-3794 |
False warning for MISRA 10.1/10.2 when commutative binary operands swapped |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
|
In certain cases, the compiler could emit an unwarranted MISRA diagnostic about type conversion. This would occur when using a commutative binary arithmetic operator with mixed operand types. The compiler mistakenly compared one operand's type to the other type. It should have compared each type to the promoted type of the operation. |
| CODEGEN-3711 |
Uses of __strex intrinsics are deleted |
Fixed |
|
ARM_18.1.0.LTS |
|
The compiler supports synchronization primitive intrinsics, but always deletes calls to __strex, __strexb, __strexh, and __strexd.
|
| CODEGEN-3619 |
pragma triggers false MISRA-C:2004 19.1/A warning |
Fixed |
|
ARM_18.1.0.LTS |
N/A |
Certain pragmas appearing prior to #include statements, such as #pragma RESET_MISRA, would cause MISRA warning 19.1/A to be issued:
MISRA-C:2004 19.1/A: #include statements in a file should only be preceded by other preprocessor directives or comments |
| CODEGEN-3595 |
Stack usage under reports stack amount used because it fails to handle function aliases |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.2.LTS |
|
CCS Stack Assistant did not accurately track aliased functions-- functions whose definitions are represented by a different symbol name. Now, the alias function will be used to determine stack size correctly, and the aliased function call name will be replaced with its alias. Currently, the Stack Assistant GUI is not capable of showing both the aliased and alias function names for calls to aliased functions-- this will require a future update. |
| CODEGEN-2373 |
Internal linker error triggered by function alias |
Fixed |
|
ARM_18.1.0.LTS |
|
Linker sometimes generates "Assertion failed" message and aborts. |
| CODEGEN-2320 |
ARM compiler fails to truncate scaled offset to byte |
Fixed |
|
ARM_18.1.0.LTS |
Compile with --opt_level=off. This is not an optimization bug; however, the bug does not manifest at --opt_level=off. |
The compiler matches X[(unsigned char)(Y >> 16)] with an indexed addressing mode, but it can't because that doesn't truncate the array index to 8 bits.
|
| CODEGEN-2257 |
Using --no_stm may discard regsave debugging information |
Fixed |
ARM_18.1.0.LTS |
ARM_18.1.0.LTS |
Don't use --no_stm unless you are sure it is necessary |
When using the --no_stm silicon workaround option for Cortex-R4, some debugging information may be lost, leading to the debugger having trouble unwinding functions, and thus being unable to show the call stack. |
| CODEGEN-1979 |
Statements before declarations with no white space (aggravated by macros) may cause incorrect parser error |
Fixed |
|
ARM_18.1.0.LTS |
Do not start any statement in the left-most column
Rearrange your code so that there are no statements before declarations. |
C99 and C++ allow statements before declarations in functions. This is not allowed by the C89 language, but as an extension, the TI compiler allows such statements in relaxed mode. However, in certain circumstances, the compiler may emit the 'error: expected "}"' for otherwise legal code which has statements before declarations.
This problem can only occur in relaxed C89 mode (which is the default mode), and 1) you have a function with statements that start in the left-most column, or 2) you use macros where the macro body contains C code with statements before declarations. |
| SDSCM00051067 |
Width-modified LDR/STREX instructions should be rejected on V6 |
Fixed |
|
ARM_18.1.0.LTS |
|
While LDREX and STREX are available on v6, all of the other EX instructions aren't available until v6k, which we do not support. For TI hardware, we begin to support these instructions in v7. The assembler should reject the instructions LDREXH, LDREXB, LDREXD, STREXH, STREXB, and STREXD for v6, including v6M0. We already treat CLREX correct and reject it for v6. |
| SDSCM00051066 |
Should reject MLS on pre-Thumb-2 devices |
Fixed |
|
ARM_18.1.0.LTS |
|
MLS is a Thumb2 instruction; it should be rejected on earlier architectures, including Cortex-M0 |
| SDSCM00047902 |
Predefined macro __TI_FPv4SPD16_SUPPORT__ should be __TI_FPV4SPD16_SUPPORT__ |
Fixed |
|
ARM_18.1.0.LTS |
|
|
| SDSCM00046352 |
Disassembler fails to emit certain instructions in UAL form |
Fixed |
|
ARM_18.1.0.LTS |
|
For certain instructions combining the S flag and a condition code, UAL requires the S to appear before the condition code, but the disassembler puts it afterward, in the pre-UAL style.
|
| SDSCM00043877 |
Emit error message when objects of size 512MB or larger truncated |
Fixed |
|
ARM_18.1.0.LTS |
N/A |
Due to an internal limitation, the code generation tools cannot presently allocate objects of size 512 MB or larger. When such objects are declared in the code, they were silently truncated and compilation continued without any diagnostics. |
| SDSCM00043334 |
Should reject illegal MOVS instruction which cannot set status |
Fixed |
|
ARM_18.1.0.LTS |
|
The assembler accepts instructions like "MOVS R0, R10" in thumb mode, but should not. There is no instruction which can perform this move while setting the status bits. |
| SDSCM00037227 |
Bad disassembly for VMRS APSR_nzcv, FPSCR |
Fixed |
|
ARM_18.1.0.LTS |
|
The ARM disassembler mistakenly disassembles "VMRS APSR_nzcv, FPSCR" as "VMRS PC, FPSCR" |
| SDSCM00037086 |
ARM assembler allows incorrect VFP registers for some instructions on D16 VFP architectures |
Fixed |
|
ARM_18.1.0.LTS |
|
For devices with VFP D16, the assembler should not allow instructions using registers D16-D31, but it does. |
