| CODEGEN-4251 |
ECC section names are randomly assigned |
Fixed |
ARM_16.9.3.LTS |
ARM_18.1.0.LTS |
|
This happens in 16.9.X.LTS because the ECC initialization code iterates over an unsorted list. This list's order happens to be non-deterministic. The ECC code was refactored significantly before the 17.3 branch, and now uses a set, which is always ordered. Thus, the problem will not occur in 17.3.0.STS or any release thereafter. We do not plan to address this for the 16.9.X.LTS branch. |
| CODEGEN-3880 |
Compiler generates invalid instruction with VFP registers |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
No practical workaround |
When using --float_support, it is sometimes possible for VFP registers to show up in regshift operands. If you do not get an error from the assembler, you are not suffering from this bug. |
| CODEGEN-3858 |
OFD gets DIE attribute offset wrong when using --dwarf_display=none,dinfo |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
If you use --dwarf_display=none,dinfo, use --dwarf_display=none,dinfo,types instead |
You can use OFD to display the DWARF debugging information in your object files by using the option '--dwarf' (or -g). You can narrow the categories of DWARF information displayed by using the '--dwarf_display' option. If you use the option --dwarf_display=none,dinfo you will see the DWARF DIE objects in the .dwarf_info section, but you will not see any DW_AT_type attributes unless you also use the "types" flag. This is not a bug. However, when OFD skips a DW_AT_type attribute, it displays the offset of the skipped DW_AT_type for the next attribute instead of the next attribute's correct offset. |
| CODEGEN-3801 |
Linker crashes with INTERNAL ERROR (unhandled exception) |
Fixed |
ARM_17.9.0.STS, ARM_15.12.6.LTS, ARM_16.9.4.LTS |
ARM_18.1.0.LTS |
|
The linker experiences a segmentation fault when there is a reference from a debug section to a symbol without a section (for example, an absolute symbol). |
| CODEGEN-3711 |
Uses of __strex intrinsics are deleted |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
|
The compiler supports synchronization primitive intrinsics, but always deletes calls to __strex, __strexb, __strexh, and __strexd.
|
| CODEGEN-3619 |
pragma triggers false MISRA-C:2004 19.1/A warning |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
N/A |
Certain pragmas appearing prior to #include statements, such as #pragma RESET_MISRA, would cause MISRA warning 19.1/A to be issued:
MISRA-C:2004 19.1/A: #include statements in a file should only be preceded by other preprocessor directives or comments |
| CODEGEN-3597 |
ELF header field e_phoff should be 0 when no program header is present |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.6.0.STS |
ARM_17.9.0.STS |
|
ELF header field e_phoff should be 0 when no program header is present, and ELF header field e_shoff should be 0 when no section headers are present. |
| CODEGEN-3593 |
The ARM User Guide has incorrect prototypes for _smuad, _smuadx, _smusd, and _smusdx |
Fixed |
ARM_16.9.0.LTS |
ARM_17.9.0.STS |
|
The intrinsics are documented as taking 3 parameters with the 3rd being an accumulator. These instructions do not perform an accumulation and therefore only accept 2 arguments:
int dst = _smuad(int src1, int src2) |
| CODEGEN-2373 |
Internal linker error triggered by function alias |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
|
Linker sometimes generates "Assertion failed" message and aborts. |
| CODEGEN-2372 |
C2000 hex utility emits spurious warning about creating an extra output file |
Fixed |
ARM_17.6.0.STS |
ARM_17.9.0.STS |
Ignore the warning or suppress it with option --diag_suppress=21117. |
The Hex utility sometimes emits spurious warnings about writing data to auto-generated files. |
| CODEGEN-2371 |
Compiler library automatic build with mklib fails |
Fixed |
ARM_17.6.0.STS |
ARM_17.9.0.STS |
Add quotes around argument to offending 'echo' command in lib/src/Makefile of the tool's installation. |
|
| CODEGEN-2320 |
ARM compiler fails to truncate scaled offset to byte |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
Compile with --opt_level=off. This is not an optimization bug; however, the bug does not manifest at --opt_level=off. |
The compiler matches X[(unsigned char)(Y >> 16)] with an indexed addressing mode, but it can't because that doesn't truncate the array index to 8 bits.
|
| CODEGEN-2286 |
palign(8) of .init_array messes up __TI_INITARRAY_Limit address |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_17.9.0.STS |
In the linker command file, replace
.init_array > FLASH, palign(8), fill = 0xffffffff
with the following GROUP statement:
GROUP
{
.init_array
} > FLASH, palign(8)
The palign(8) on GROUP will ensure that any required padding is added after .init_array. However, both the size of .init_array and the value of __TI_INITARRAY_Limit remain unchanged. |
Applying palign(8) to .init_array caused __TI_INIT_ARRAY_Limit to be set to the end of .init_array including the padding. This broke RTS startup code responsible for calling constructors because the table of constructors now includes invalid data. This bug has been fixed and __TI_INIT_ARRAY_Limit is no longer affected by padding. |
| CODEGEN-2257 |
Using --no_stm may discard regsave debugging information |
Fixed |
ARM_5.2.7, ARM_16.6.0.STS, ARM_15.12.0.LTS, ARM_17.6.0.STS, ARM_18.1.0.LTS |
ARM_17.9.0.STS |
Don't use --no_stm unless you are sure it is necessary |
When using the --no_stm silicon workaround option for Cortex-R4, some debugging information may be lost, leading to the debugger having trouble unwinding functions, and thus being unable to show the call stack. |
| CODEGEN-2209 |
Link error with gcc debug information |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.3.0.STS |
ARM_17.6.0.STS |
None |
When linking against GCC code, a project failed to build due to a relocation error, generating the message "fatal error #10232". Specifically, the problem was caused by debug information left in the GCC object file for eliminated comdat sections. GCC puts debug information into a common section called .debug_info. Once the comdat section was eliminated, the debug symbol pointed to a deleted section, causing an error in the TI linker. |
| CODEGEN-2123 |
Compiler manuals incorrectly document option --gen_preprocessor_listing as --gen_parser_listing |
Fixed |
ARM_17.3.0.STS |
ARM_17.3.0.STS |
|
The correct name of the compiler option is --gen_preprocessor_listing. |
| CODEGEN-2119 |
Stack usage assistant call graph misses callee relationship for some direct calls |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.6.0.STS |
ARM_17.6.0.STS |
|
The Object File Display utility failed to detect function callees when generating call graph information for functions that contain nested blocks. |
| CODEGEN-2113 |
Hex utility mishandles space in directory name of output file |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.6.0.STS |
ARM_17.6.0.STS |
Use directory names without spaces for output files. |
The hex utility did not correctly handle spaces in output directory and file names. |
| CODEGEN-2098 |
Temp filename collisions on Windows with many parallel invocations |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.3.0.STS |
ARM_17.6.0.STS |
|
In some cases with a large number of compilations in parallel on Windows, the compiler could create temporary files with colliding names, resulting in strange compilation failures. |
| CODEGEN-2065 |
Compiler documentation implies --check_misra compiler option not needed if pragma used |
Fixed |
ARM_17.3.0.STS |
ARM_17.3.0.STS |
|
The --check_misra compiler option is required to enable MISRA checking even if the CHECK_MISRA pragma is used. |
| CODEGEN-2060 |
Even though option --buffer_diagnostics is not used, compiler issues diagnostic that says it is deprecated |
Fixed |
ARM_16.9.0.LTS, ARM_16.12.0.STS |
ARM_17.3.0.STS |
None |
The --buffer_diagnostics compiler option was deprecated as of MCU compilers v16.6.0.STS because this setting became the default behavior for the compiler. However, the option was passed to the linker and the linker issued a remark stating the option was deprecated. |
| CODEGEN-2053 |
Compiler incorrectly reorders struct assign for small, volatile structs with bit-fields |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_16.12.0.STS |
ARM_17.3.0.STS |
Use optimization level 0 or off (option --opt_level) |
For a very specific optimization, the optimizer may drop a volatile qualifier from a struct assignment. In some cases, the compiler may later perform an incorrect optimization, most commonly incorrectly reordering volatile assignments.
This bug can only happen in a function compiled with optimization level 1 or higher which contains both of the following: 1) A struct assign where the destination is volatile, and the source is a known constant, and the struct contains a bit-field, and the struct is of size "int" or smaller. 2) Any bit-field access (read or write) other than as part of a struct assign or initialization expression. That is, the name of the bit-field is present in the access expression. Note that the optimizer can create this situation by inlining functions, so 1 and 2 might be in different functions in the source code.
Consider a tree x = y where x and y are of type struct S. If the value of y is known at compile time (e.g. a const value), the optimizer will try to turn the struct constant into an integer constant (possibly combining bit-fields) and rewrite the tree to look like this: "(unsigned *)x = 32;" However, if y is volatile, that should be "*(volatile unsigned *)x = 32;" Because the access is not volatile, instruction scheduling could cause this instruction to drift past nearby volatile accesses. |
| CODEGEN-2050 |
Use of -o4 causes linker XML map file to have missing input_file entries |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_16.12.0.STS |
ARM_17.3.0.STS |
|
|
| CODEGEN-2047 |
CMSIS Core v5 is not compliant with TI ARM Compiler |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_16.12.0.STS |
ARM_17.3.0.STS |
The __INLINE macro in the TI compiler RTS linkage.h is no longer used and can be removed. |
CMSIS v5 defines the macro __INLINE, which interferes with the TI compiler RTS definition of the same macro in linkage.h. |
| CODEGEN-1979 |
Statements before declarations with no white space (aggravated by macros) may cause incorrect parser error |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.6.0.STS |
ARM_18.1.0.LTS |
Do not start any statement in the left-most column
Rearrange your code so that there are no statements before declarations. |
C99 and C++ allow statements before declarations in functions. This is not allowed by the C89 language, but as an extension, the TI compiler allows such statements in relaxed mode. However, in certain circumstances, the compiler may emit the 'error: expected "}"' for otherwise legal code which has statements before declarations.
This problem can only occur in relaxed C89 mode (which is the default mode), and 1) you have a function with statements that start in the left-most column, or 2) you use macros where the macro body contains C code with statements before declarations. |
| CODEGEN-1976 |
Value of __cplusplus is wrong |
Fixed |
ARM_15.12.0.LTS, ARM_5.2.0B1, ARM_16.9.0.LTS, ARM_16.12.0.STS |
ARM_17.3.0.STS |
If possible, use the -ps or --strict_ansi options. This mode will use the strict definition of __cplusplus, which is 199711L. |
Our parser mimicked G++ behavior for the value of this macro in relaxed ANSI mode. This reproduced a bug in G++ versions v.4.7 and v.4.3 that has since been fixed. |
| CODEGEN-1705 |
Compiler documentation and RTS disagree on function names _TI_start_pprof_collection and _TI_stop_pprof_collection |
Fixed |
ARM_16.9.0.LTS, ARM_16.12.0.STS |
ARM_16.12.0.STS |
|
|
| CODEGEN-1656 |
Using --gen_profile_info does not work with -o4 |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.6.0.STS |
ARM_17.6.0.STS |
Lower the optimization level to -o3. |
Previously, link time optimization failed when profiling options --gen_profile_info and use_profile_info were specified in combination with the --opt_level=4 option. The errors were because profiling options were not supported when used in combination with --opt_level=4.
Application profiling during whole program optimization is now supported. Profiling options --gen_profile_info and --use_profile_info may now be combined with --opt_level=4. |
| SDSCM00052878 |
Documentation error: #pragma pack should be lower case |
Fixed |
ARM_15.12.1.LTS, ARM_16.3.0.STS, ARM_16.12.0.STS |
ARM_16.12.0.STS |
|
|
| SDSCM00051067 |
Width-modified LDR/STREX instructions should be rejected on V6 |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
|
While LDREX and STREX are available on v6, all of the other EX instructions aren't available until v6k, which we do not support. For TI hardware, we begin to support these instructions in v7. The assembler should reject the instructions LDREXH, LDREXB, LDREXD, STREXH, STREXB, and STREXD for v6, including v6M0. We already treat CLREX correct and reject it for v6. |
| SDSCM00051066 |
Should reject MLS on pre-Thumb-2 devices |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
|
MLS is a Thumb2 instruction; it should be rejected on earlier architectures, including Cortex-M0 |
| SDSCM00047902 |
Predefined macro __TI_FPv4SPD16_SUPPORT__ should be __TI_FPV4SPD16_SUPPORT__ |
Fixed |
ARM_15.12.0.LTS, ARM_5.2.0B1, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
|
|
| SDSCM00046352 |
Disassembler fails to emit certain instructions in UAL form |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
|
For certain instructions combining the S flag and a condition code, UAL requires the S to appear before the condition code, but the disassembler puts it afterward, in the pre-UAL style.
|
| SDSCM00043877 |
Emit error message when objects of size 512MB or larger truncated |
Fixed |
ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
N/A |
Due to an internal limitation, the code generation tools cannot presently allocate objects of size 512 MB or larger. When such objects are declared in the code, they were silently truncated and compilation continued without any diagnostics. |
| SDSCM00043334 |
Should reject illegal MOVS instruction which cannot set status |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
|
The assembler accepts instructions like "MOVS R0, R10" in thumb mode, but should not. There is no instruction which can perform this move while setting the status bits. |
| SDSCM00037227 |
Bad disassembly for VMRS APSR_nzcv, FPSCR |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
|
The ARM disassembler mistakenly disassembles "VMRS APSR_nzcv, FPSCR" as "VMRS PC, FPSCR" |
| SDSCM00037086 |
ARM assembler allows incorrect VFP registers for some instructions on D16 VFP architectures |
Fixed |
ARM_15.12.0.LTS, ARM_16.9.0.LTS, ARM_17.9.0.STS |
ARM_18.1.0.LTS |
|
For devices with VFP D16, the assembler should not allow instructions using registers D16-D31, but it does. |
