| ID |
Summary |
State |
Reported In Release |
Target Release |
Workaround |
Release Notes |
| CODEGEN-4700 |
Incorrect diagnostic when using macro that comes from macro library |
Open |
ARM_16.9.4.LTS |
|
|
|
| CODEGEN-4667 |
Assembler macro with temp label causes incorrect error messages to be emitted |
Accepted |
ARM_16.9.7.LTS |
|
|
|
| CODEGEN-3924 |
Automatic RTS build fails when specific library name is seen by the linker |
Planned |
ARM_16.9.3.LTS |
|
Link against libc.a instead |
When the linker is asked to link against a specific rts library (e.g. rtsv4_A_be_abi.lib), but that library does not exist (needs to be built), the linker emits an error rather than attempt to build the library. |
| CODEGEN-3843 |
Use of cdecls and --advice:power=all causes very strange diagnostics |
Accepted |
ARM_16.9.4.LTS |
|
|
|
| CODEGEN-2215 |
RTS source code comments regarding multiple threads not qualified to C6000-only |
Accepted |
ARM_16.9.2.LTS |
|
|
|
| SDSCM00052872 |
#pragma LOCATION and palign do not work together |
Open |
ARM_16.9.0.LTS |
|
One workaround is to use specific placement in the linker command file. In the C code, replace the #pragma LOCATION with a #pragma DATA_SECTION ...
#pragma DATA_SECTION(device_fw_info_ptr, "for_device");
And in the linker command file, replace the whole .TI.bound line with this ...
for_device > 0x00018000, palign(8), fill = 0xffffffff
|
|
| SDSCM00052868 |
Automatic library build fails when an exact library name is used |
Open |
ARM_16.9.0.LTS |
|
Don't specify the name of the library. |
|
| SDSCM00052849 |
Compiler and assembler disagree on format for IT instruction |
Open |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00052780 |
The armhex command does not handle spaces in the name of the output binary |
Open |
ARM_16.9.0.LTS |
|
|
|
| CODEGEN-1458 |
Consider splitting up unified_locale.cpp to save code space |
Open |
ARM_16.9.0.LTS |
|
|
|
| CODEGEN-1445 |
Compiler inserts unnecessary register copy |
Open |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00051660 |
When the imaginary part of z is INFINITY, cprojf(z) is NOT equivalent to INFINITY + I * copysign(0.0, cimagf(z)) |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00051484 |
Compiler does not respect partial overrides in C99 designated initializers |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00051367 |
Disable diagnostic 1558 (--float_operations_allowed diagnostic) in standard header files |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00051165 |
Should accept "LDRD R8,[R1]" in Thumb-2 mode |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00051114 |
Missing half-precision float conversion functions |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00051113 |
Missing __aeabi_read_tp |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00051111 |
Missing AEABI_COMPATIBILITY_MODE link-time constants |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00051086 |
Assembler accepts but mistranslates BLLT in v7 thumb mode |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00051069 |
Should allow "ADD R0, R1, #0xfff" for v6m0 |
Accepted |
ARM_16.9.0.LTS |
|
Use the syntax "ADDW R0, R1, #0xfff" instead. |
|
| SDSCM00051065 |
Should accept 2-operand SUB SP in Thumb1/UAL mode |
Accepted |
ARM_16.9.0.LTS |
|
Use ADD SP, SP, #<imm> instead
|
|
| SDSCM00050861 |
Should accept 2-operand add in ARM mode |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00050499 |
The .label assembler directive should not be accepted when assembling for ELF. |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00050131 |
Local struct with non-constant initializer treated as static scope variable |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00049911 |
__aeabi_dcmpun returns 1 for Inf and -Inf |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00049280 |
Ill advised enum scalar usage gets MISRA diagnostic, but similar usage of enum array does not |
Open |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00049278 |
Array that is correctly initialized erroneously gets a MISRA diagnostic about size not being specified |
Open |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00048267 |
Warning generated when using __curpc intrinsic on Thumb 2 |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00047077 |
Incorrectly reduced double constant to float when ultimate destination is short |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00046102 |
MISRA 12.8 and MISRA 10.5 false positives |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00046074 |
Cortex-M0 library lacks uread4, etc. |
Open |
ARM_16.9.0.LTS |
|
If using the TI compiler, the TI compiler doesn't call any of these functions, so no workaround should be necessary.
If using any other vendor's compiler and linking with the TI toolchain, link with the other vendor's toolchain. |
|
| SDSCM00040934 |
Structure is not initialized correctly when using -o2 or -o3 optimization |
Accepted |
ARM_16.9.0.LTS |
|
The initialization will have to be done at run-time, through a __sti initialization routine. You can see this routine when compiling without optimization. To workaround the compiler removing this initialization routine, initialize the object at the beginning of main:
Info2.mSize = ((unsigned)_end_isr_stack - (unsigned)_start_isr_stack);
|
|
| SDSCM00040523 |
The _ssat16 intrinsic allows literals in the range of 0-31, but the SSAT16 instruction only accepts values from 1-16 |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00040522 |
_ssatl intrinsic allows 3rd argument to be 0 resulting in an assembler error. |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00039636 |
When creating a partial linked ELF object file, the linker uses virtual addresses instead of relative addresses. |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00039626 |
ARM assembler does not issue a warning for PC-relative loads when --embedded_constants=off |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00037008 |
Linker outputting wrong build attribute name for EABI TAG_VFP_arch on ARM targets |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00036874 |
Section relative ELF symbol values in partially linking object files should hold the section offset for the symbol |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00018691 |
Linker gives misleading warning when dot expressions used in SECTION directive for .stack section |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00014430 |
calloc doesn't check arguments to make sure the requested size is reasonable |
Accepted |
ARM_16.9.0.LTS |
|
|
|
| SDSCM00008685 |
DWARF does not correctly represent variables stored in register pairs |
Planned |
ARM_16.9.0.LTS |
|
Although 'var1' and 'var2' are shown to be in single registers, a
debugger could determine that they are actually stored in register
pairs by looking at the type of the variables:
[00000113] DW_TAG_base_type
DW_AT_name long long
DW_AT_encoding 0x5
DW_AT_byte_size 0x8
The base type indicates that the size of the variables is 0x8 bytes.
Since a single register can only store 0x4 bytes of information, it
would take two registers to hold this values.
On TI architectures, values stored in multiple registers are always
stored in consecutive registers. Thus, the debugger would know that
if the entire value could not fit in A4, the rest of the value must be
in A5. A5 would contain the upper 32 bits of the value.
|
|
| SDSCM00008543 |
Forward reference in .space generates an internal error |
Accepted |
ARM_16.9.0.LTS |
|
none
|
|
| SDSCM00008248 |
Compilers on PC will not work without TMP set |
Accepted |
ARM_16.9.0.LTS |
|
Set the TMP environment variable, even if just set to . (current directory)
|
|
