Readme for C2000 Code Generation Tools v22.6.3.LTS
Table of Contents
LTS Release
The C2000 CGT v22.6.x.LTS release is an LTS release.
Definitions
Short-Term Support (STS) release: All STS branches will be made reactive upon creation. A patch release for this branch will only be created for production stop issues and will only contain fixes for the production stop issues. For all other issues, users are advised to wait for the next STS branch, which may also contain new features. STS releases will occur approximately every 3 months up until the first LTS release in a release stream.
Long-Term Support (LTS) release: The LTS branch will be active upon creation. The branch will be active for at least 2 years. Production stop defects will be addressed within 2 weeks of being reported. Critical defects will be addressed within 90 days. Defect repairs are proactively applied to each release stream. The LTS release is intended for customers to lock down on tools.
Compiler Downloads and Documentation
Documentation for the “TI C2000 Optimizing Compiler User’s Guide” and the “TI C2000 Assembly Language User’s Guide” is available online at:
https://www.ti.com/tool/C2000-CGT
TI E2E Community
Questions concerning TI Code Generation Tools can be posted to the TI E2E Community forums at:
The following is the top-level webpage for all of TI’s Code Generation Tools.
If submitting a defect report, please attach a scaled-down test case with command-line options and the compiler version number to allow us to reproduce the issue easily.
Defect Tracking Database
Compiler defect reports can be tracked at the Development Tools bug database at:
New Features:
New option --fp_single_precision_constant treats unsuffixed floating point constants as 32-bit
New option --fp_single_precision_constant treats unsuffixed floating-point constants as single precision instead of implicitly converting them to double-precision constants.
Interrupt save/restore efficiency improvement
The C2000 compiler now only saves/restores any registers that were used in an interrupt service routine (ISR). Additionally, if an ISR makes function calls, then all save-on-call (SoC) registers will get saved/restored. For FPU compilations, the RB register is saved/restored for all low priority ISRs, however, for high priority ISRs, the RB register is only saved/restored if the ISR may use an RPTB instruction.
The compiler user guide states:
“If a C/C++ interrupt routine does not call any other functions, only those registers that the interrupt handler uses are saved and restored”
However, prior to this update, above has not been the case since at least release 6.4 and the actual behavior has been to save/restore all SoC registers as long as any single SoC register was used.
Performance improvements CLA
CLA support enabled for generating MMACF32||MMOV32
The CLA compiler has a new feature for generating parallel MMACF32 with MMOV32 instructions. Generating MMACF32||MMOV32 requires --opt_level=2 or higher and loop unrolling is recommneded for creating more opportunities for the parallel MMACF32 with MMOV32. For example:
// result, buff[], and coef[] are float
interrupt void Cla1Task1 ( void )
{
result = 0.0f;
int16_t i;
#pragma UNROLL(20)
for(i = 20; i > 0; i–)
{
buff[i] = buff[i-1];
result += coef[i] * buff[i];
}
result += coef[0] * buff[0];
}CLA MRn loads of unsigned short are more efficient
The CLA compiler now generates more efficient loads of unsigned short variables to the 32-bit MRn register. Previously the compiler generated below including the redundant zero extending shifts:
{The CLA compiler instead generates only below which already zero extends:
// unsigned a,b;
// a = b;
MMOVZ16 MR0,@b
MLSL32 MR0,#16
MLSR32 MR0,#16
}
{
// unsigned a,b;
// a = b;
MMOVZ16 MR0,@b
}
Performance improvements C28
Improvements in reducing register spilling
The C2000 compiler has a new feature for reducing register spilling. During register allocation (selection of registers), if no registers are available, then the compiler must spill a register to memory (or another register) in order to make it available for register allocation.
A new optimization pass has been enabled for compilations with --opt_level=2 or higher and --float_support=fpu32/fpu64. If register spilling is detected, the compiler will generate a new instruction schedule to alleviate register pressure (shorten register use lifetimes) which should in turn reduce register spilling.Keep global float/double variables in registers
The C2000 compiler has a new optimization that will attempt to keep global float/double variables in registers if the device has fpu register support. As a simple example, prior to this optimization, below loop:
float flt;
would generate this assembly that loads/stores the float variable from memory during each iteration (with --opt_level=2):
for(i=0;i<2000;i++)
{
flt = flt + flt;
}
MOVL XAR6,#1999
which now is improved to this sequence that keeps the float variable in R2H during the loop:
loop:
MOVW DP,#flt
MOV32 R0H,@flt
MOV32 R1H,@flt
ADDF32 R0H,R0H,R1H
NOP
MOV32 @flt,R0H
BANZ loop,AR6—
MOVW DP,#flt
MOVL XAR6,#1999
MOV32 R2H,@flt
loop:
ADDF32 R2H,R2H,R2H
BANZ loop,AR6—If-conversion improvements
The current if-conversion optimizations for the C2000 compiler have been extended with below additional use cases.
This sequence with --opt_level=off,0,1:extern float f1, f2;
with --opt_level=2,3,4 is now generated without the branches:
float foo(float cond)
{
return cond > 1.0f ? f1 : f2;
}
||foo||:
CMPF32 R0H,#16256
MOVST0 ZF, NF
B ||label1||,LEQ
MOVW DP,#||f1||
MOV32 R0H,@||f1||
B ||label2||,UNC
||label1||:
MOVW DP,#||f2||
MOV32 R0H,@||f2||
||label2||:
LRETR||foo||:
CMPF32 R0H,#16256
MOVW DP,#||f1||
MOV32 R0H,@||f1||,GT
MOVW DP,#||f2||
MOV32 R0H,@||f2||,LEQ
LRETR
This sequence:MOVL XAR4,#||t||
is instead generated without the branch:
TBIT *+XAR4[0],#1
MOVB XAR0,#8,TC
B ||label||,TC
MOVB XAR0,#0
label:MOVL XAR4,#||t||
MOVB XAR0,#0
TBIT *+XAR4[0],#1
MOVB XAR0,#8,TC
And this sequence:
TBIT *+XAR5[0],#2
is instead generated without the branch:
B label,NTC
MOV AH,AR0
ORB AH,#0x04
MOVZ AR0,AH
label:TBIT *+XAR5[0],#2
MOV AH,AR0
ORB AH,#0x04
MOV AR0,AH,TC
Improved loads of 16-bit constants to ACC register
Below accumulator load of 16-bit constants:
MOVL XAR4,#256
is now directly loaded to the ACC register:
MOVL ACC,XAR4
MOV ACC,#256
RTS library routine fmodf() now has faster tmu relaxed implementation using __fmodf intrinsic
The current RTS library support for fmodf() has been extended with a faster tmu implementation using new intrinsic __fmodf().
Below intrinsic is available with option --tmu_support=tmu0,tmu1.float __fmodf(float x, float y); /* return fmodf(x,y) */
If the user specifies --fp_mode=relaxed in combination with the --tmu_support=tmu0,tmu1 option in the compiler command line, then the following RTS function will make use of the new __fmodf intrinsic:float fmodf(float x, float y);
Hex tool: new options --boot_align_sect and --boot_block_size=size
- --boot_align_sect
New option --boot_align_sect will cause the hex tool to adjust the default boot record limit size based on section alignment (for alignment > 1). For example, if an output section has ALIGN(16), then the boot record size will be adjusted from default value of 0xFFFE to 0xFFF0. - --boot_block_size=size
New option --boot_block_size=size allows overriding the hex utility default boot block size. (ARM default is 0xFFFF which is not supported by C28 FLASH API).
For use with the C28 FLASH API and the C28 on-chip bootloader:
c28 hex boot files: hex2000 current-boot-options –boot_align_sect
arm hex boot files: armhex current-boot-options –boot_align_sect –boot_block_size=0xFFFE
Resolved defects
Resolved defects in v22.6.3.LTS:
| ID | Summary |
|---|---|
| CODEGEN-14346 | Cannot use char16_t for 16-bit wide string literals |
| CODEGEN-14342 | Dwarf call frame information contains frame description entries with instructions with the wrong address |
| CODEGEN-14324 | Compiler fails with INTERNAL ERROR: opt2000 experienced a segmentation fault |
| CODEGEN-14240 | C28 silicon bug workaround: FastIntDiv or DIVF64 instruction preceded by certain FPU 2p operations |
| CODEGEN-13621 | Compiler generates illegal parallel instruction that causes assembler to issue a valid error |
| CODEGEN-13483 | Right shift of int40_t value converted from float causes compiler to fail with INTERNAL ERROR: no match for SRL |
| CODEGEN-13346 | C28 intrinsic, __iexp2(float), uses TMU1 instruction IEXP2F32 which has accuracy issues when base/exponent are outside specified ranges |
| CODEGEN-13286 | long long or double value passed as 10th argument to a function that returns a struct may be corrupted |
| CODEGEN-12562 | Compiler incorrectly optimizes implicit cast to pointer expression (int32)(uint16+constant) to within expression ((int32)uint16+constant) |
| CODEGEN-12500 | Optimizer incorrectly distributes a float type into an unsigned integer expression of smaller size |
| CODEGEN-12282 | Missing warning for C89 with integer literal too large for long |
| CODEGEN-12260 | C2000 MOVDL instruction tries to simultaneously access two memory locations across DP boundary |
| CODEGEN-11909 | Documentation needs to state that building C++ files with –abi=eabi forces runtime type identification (RTTI) to be included |
| CODEGEN-10306 | For EABI cinit copy “compression”, the linker incorrectly sets the number of bytes to copy for smaller copy initialization sizes |
| CODEGEN-9407 | Flexible array of structs does not correctly initialize last element with implicitly initialized struct members. |
Known defects (dynamic)
The following link will lead to an updated list of known defects in this release: