Readme for C2000 Code Generation Tools v22.6.0.LTS

Table of Contents

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LTS Release

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The C2000 CGT v22.6.0.LTS release is an LTS release.

Definitions

• Short-Term Support (STS) release: All STS branches will be made reactive upon creation. A patch release for this branch will only be created for production stop issues and will only contain fixes for the production stop issues. For all other issues, users are advised to wait for the next STS branch, which may also contain new features. STS releases will occur approximately every 3 months up until the first LTS release in a release stream.

• Long-Term Support (LTS) release: The LTS branch will be active upon creation. The branch will be active for at least 2 years. Production stop defects will be addressed within 2 weeks of being reported. Critical defects will be addressed within 90 days. Defect repairs are proactively applied to each release stream. The LTS release is intended for customers to lock down on tools.

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Compiler Downloads and Documentation

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Documentation for the “TI C2000 Optimizing Compiler User’s Guide” and the “TI C2000 Assembly Language User’s Guide” is available online at:

https://www.ti.com/tool/C2000-CGT

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TI E2E Community

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Questions concerning TI Code Generation Tools can be posted to the TI E2E Community forums at:

• E2E Development Forum

The following is the top-level webpage for all of TI’s Code Generation Tools.

• Code Generation Tools Landing Page

If submitting a defect report, please attach a scaled-down test case with command-line options and the compiler version number to allow us to reproduce the issue easily.

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Defect Tracking Database

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Compiler defect reports can be tracked at the Development Tools bug database at:

https://sir.ext.ti.com/

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New Features:

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New option --fp_single_precision_constant treats unsuffixed floating point constants as 32-bit

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New option --fp_single_precision_constant treats unsuffixed floating-point constants as single precision instead of implicitly converting them to double-precision constants.

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Interrupt save/restore efficiency improvement

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The C2000 compiler now only saves/restores any registers that were used in an interrupt service routine (ISR). Additionally, if an ISR makes function calls, then all save-on-call (SoC) registers will get saved/restored. For FPU compilations, the RB register is saved/restored for all low priority ISRs, however, for high priority ISRs, the RB register is only saved/restored if the ISR may use an RPTB instruction.

The compiler user guide states:
“If a C/C++ interrupt routine does not call any other functions, only those registers that the interrupt handler uses are saved and restored”
However, prior to this update, above has not been the case since at least release 6.4 and the actual behavior has been to save/restore all SoC registers as long as any single SoC register was used.

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Performance improvements CLA

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• CLA support enabled for generating MMACF32||MMOV32
  The CLA compiler has a new feature for generating parallel MMACF32 with MMOV32 instructions. Generating MMACF32||MMOV32 requires --opt_level=2 or higher and loop unrolling is recommneded for creating more opportunities for the parallel MMACF32 with MMOV32. For example:
  
  

   // result, buff[], and coef[] are float
   interrupt void Cla1Task1 ( void )
   {
        result = 0.0f;
        int16_t i;
        #pragma UNROLL(20)
        for(i = 20; i > 0; i–)
        {
             buff[i] = buff[i-1];
             result += coef[i] * buff[i];
        }
        result += coef[0] * buff[0]; 
   } 

• CLA MRn loads of unsigned short are more efficient
  The CLA compiler now generates more efficient loads of unsigned short variables to the 32-bit MRn register. Previously the compiler generated below including the redundant zero extending shifts:
  

   {
        // unsigned a,b;
        // a = b;
        MMOVZ16 MR0,@b
        MLSL32 MR0,#16
        MLSR32 MR0,#16
   } 

  The CLA compiler instead generates only below which already zero extends:
  

   {
        // unsigned a,b;
        // a = b;
        MMOVZ16 MR0,@b
   } 

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Performance improvements C28

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• Improvements in reducing register spilling
  The C2000 compiler has a new feature for reducing register spilling. During register allocation (selection of registers), if no registers are available, then the compiler must spill a register to memory (or another register) in order to make it available for register allocation.
  
  A new optimization pass has been enabled for compilations with --opt_level=2 or higher and --float_support=fpu32/fpu64. If register spilling is detected, the compiler will generate a new instruction schedule to alleviate register pressure (shorten register use lifetimes) which should in turn reduce register spilling.

• Keep global float/double variables in registers
  The C2000 compiler has a new optimization that will attempt to keep global float/double variables in registers if the device has fpu register support. As a simple example, prior to this optimization, below loop:
  

   float flt;
   for(i=0;i<2000;i++)
   {
        flt = flt + flt;
   } 

  would generate this assembly that loads/stores the float variable from memory during each iteration (with --opt_level=2):
  

        MOVL     XAR6,#1999
   loop:
        MOVW     DP,#flt
        MOV32    R0H,@flt
        MOV32    R1H,@flt
        ADDF32   R0H,R0H,R1H
        NOP
        MOV32    @flt,R0H
        BANZ     loop,AR6— 

  which now is improved to this sequence that keeps the float variable in R2H during the loop:
  

        MOVW     DP,#flt
        MOVL     XAR6,#1999
        MOV32    R2H,@flt
   loop:
        ADDF32   R2H,R2H,R2H
        BANZ     loop,AR6— 

• If-conversion improvements
  The current if-conversion optimizations for the C2000 compiler have been extended with below additional use cases.
  
  This sequence with --opt_level=off,0,1:

   extern float f1, f2;
   float foo(float cond)
   {
        return cond > 1.0f ? f1 : f2;
   }
  
   ||foo||:
        CMPF32    R0H,#16256
        MOVST0    ZF, NF
        B         ||label1||,LEQ
        MOVW       DP,#||f1||
        MOV32     R0H,@||f1||
        B         ||label2||,UNC
   ||label1||:
        MOVW       DP,#||f2||
        MOV32     R0H,@||f2||
   ||label2||:
        LRETR 

  with --opt_level=2,3,4 is now generated without the branches:

   ||foo||:
        CMPF32  R0H,#16256
        MOVW    DP,#||f1||
        MOV32   R0H,@||f1||,GT
        MOVW    DP,#||f2||
        MOV32   R0H,@||f2||,LEQ
        LRETR 

  
  This sequence:

        MOVL   XAR4,#||t|| 
        TBIT   *+XAR4[0],#1 
        MOVB   XAR0,#8,TC 
        B     ||label||,TC 
        MOVB   XAR0,#0 
   label: 

  is instead generated without the branch:

        MOVL   XAR4,#||t|| 
        MOVB   XAR0,#0 
        TBIT   *+XAR4[0],#1 
        MOVB   XAR0,#8,TC
  
  

  
  And this sequence:
  

        TBIT   *+XAR5[0],#2 
        B     label,NTC 
        MOV    AH,AR0 
        ORB    AH,#0x04 
        MOVZ   AR0,AH 
   label: 

  is instead generated without the branch:

        TBIT   *+XAR5[0],#2 
        MOV    AH,AR0 
        ORB    AH,#0x04 
        MOV    AR0,AH,TC
  
  

• Improved loads of 16-bit constants to ACC register
  Below accumulator load of 16-bit constants:
  

        MOVL XAR4,#256
        MOVL ACC,XAR4 

  is now directly loaded to the ACC register:
  

        MOV ACC,#256 

• RTS library routine fmodf() now has faster tmu relaxed implementation using __fmodf intrinsic
  The current RTS library support for fmodf() has been extended with a faster tmu implementation using new intrinsic __fmodf().
  Below intrinsic is available with option --tmu_support=tmu0,tmu1.

   float __fmodf(float x, float y); /* return fmodf(x,y) */ 

  If the user specifies --fp_mode=relaxed in combination with the --tmu_support=tmu0,tmu1 option in the compiler command line, then the following RTS function will make use of the new __fmodf intrinsic:

   float fmodf(float x, float y); 

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Hex tool: new options --boot_align_sect and --boot_block_size=size

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• --boot_align_sect
  New option --boot_align_sect will cause the hex tool to adjust the default boot record limit size based on section alignment (for alignment > 1). For example, if an output section has ALIGN(16), then the boot record size will be adjusted from default value of 0xFFFE to 0xFFF0.
  
  
• --boot_block_size=size
  New option --boot_block_size=size allows overriding the hex utility default boot block size. (ARM default is 0xFFFF which is not supported by C28 FLASH API).
  
  For use with the C28 FLASH API and the C28 on-chip bootloader:
       c28 hex boot files: hex2000 current-boot-options –boot_align_sect
       arm hex boot files: armhex current-boot-options –boot_align_sect –boot_block_size=0xFFFE
  

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Resolved defects

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Resolved defects in v22.6.0.LTS:

ID	Summary
CODEGEN-9631	CLA: Loads of 16bit signed, negative integers to MRn registers will incorrectly zero-extend by 16 bits rather than sign-extend
CODEGEN-8471	Hex utility, when splitting a section as required by the bootloader, ignores the section alignment for the second part of the split

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Known defects (dynamic)

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The following link will lead to an updated list of known defects in this release:

Known defects – dynamic

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