PinMux Release Notes

Table of Contents

Release notes for the TI PinMux Tool (v4)

Known issues from previous releases will carry over and apply to newer PinMux Tool versions unless the release notes claim the particular known issue was fixed.

PinMux Version 4.0.1543 - January 17, 2020

Bug Fixes

• J7 is no longer beta. Same pinmux data applies to J721E, DRA829, TDA4VM, AM752x.
• AM5718 and AM5716 processors are restored in this version

PinMux Version 4.0.1538 - January 6, 2020

Processors

• Released J721E super-set device, covers DRA829V and TDA4VM families (see datasheet for supported peripherals)

Bug Fixes

• AM335x and AMIC110: devicetree will now notify users to configure the SMA2 register for certain pin selections
• Remove inactive parts.

Known Issues

• AM5718 and AM5716 are missing in this version, please use v4.0.1357 release until the devices are restored

PinMux Version 4.0.1537 - Sept 20, 2019

• Added support for IWR18xx

PinMux Version 4.0.1535 - Aug 08, 2019

Processors

• Released AM5768 and AM5766 devices
• Released AM65xx device covering AM654x, AM652x families
• Released DRA80x, DRA77xP, DRA76xP devices
• Released TDA2Px ACD devices

Bug Fixes

• AM65xx and DRA80x: fixed compile issue with static keyword in RTOS output files
• AM65xx and DRA80x: fixed issue in offset calculation for main_pmx1 device tree node

PinMux Version 4.0.1532 - May 16, 2019

C2xxx MCUs

• Add F2838x device support

PinMux Version 4.0.1531 - April 24, 2019

C2xxx MCUs

• F28379D/F28379S
  • Fixed EM1SDCKE pin options for EMIF1
• F28004x
  • Switched 64PM package and 64PMQ package
  • Fixed device pin names containing “!!ERROR!!”

Processors

• All AM335x, AM437x, AMIC110, AMIC120
  • fixed incorrect register offset in device tree output
• AM437x
  • IOSET fixes for PRUSS1 ECAT to configure IN and OUT signals at the same time
  • MMC use case fix to enable input buffer on MMC_SDWP
• DRA78x, TDA3x
  • Added new IOSETs to VIN1B and VIN2B
• TDA3x
  • Add missing VIN1A hsync0 and fld0 signals in all VIN1 IOSETs

PinMux Version 4.0.1530 - Dec 20, 2018

This release contains a device data update with new devices added.

• AWR18XX Added

PinMux Version 4.0.1528 - Dec 4, 2018

Processors

all AM574x, TDA2Px, DRA75xP_DRA74xP

• added new IOSETs to SPI3 and SPI4
• bug fixes in output code generators
• updated IODelays to match the latest datasheet release
• beta tag removed as of these latest IODelay values

DRA77xP_DRA76xP

• added new IOSETs to SPI3 and SPI4

PinMux Version 4.0.1527 - Oct 31, 2018

This release contains a device data update with new devices added.

• IWR68XX Added

PinMux Version 4.0.1526 - Oct 15, 2018

This release contains a device data update with new devices added.

Newly added devices

• AM65x Family (AM6548, AM6546, AM6528, AM6527, AM6526)
• DRA80xM

all AM335x, AM437x, AMIC, and K2G

• device tree file is now in DTSI format

AM571x, DRA71x, DRA72x, DRA78x, DRA79x, TDA2Ex 17 and TDA2Ex 23

• added MANUAL4 and MANUAL5 IO Delay timing modes

PinMux Version 4.0.1522 - July 3, 2018

Processors

Newly added devices

• AMIC120 (tool folder)
• AMIC110 (renamed from AMIC11x)

all AM572x, TDA2x, DRA75x_DRA74x

• added new IOSETs to SPI3 and SPI4
• bug fixes in output code generators

DRA77xP_DRA76xP

• added nmin pin to INTC interface

DRA71x, DRA79x, TDA2Ex 17

• added new IOSETs to USB3

DRA78x, TDA3x, and DM50x

• added new IOSETs to MCASP2

AMIC110

• peripheral ECAP is now supported on AMIC110

PinMux Version 4.0.1519 - May 1 2018

Processors

Newly added devices

• AM5748_SR1.0_beta
• AM5746_SR1.0_beta
• DRA77xP / DRA76xP Beta (ACD package)
• DRA75xP / DRA74xP Beta (ABZ package)
• DRA72x_SR2.0 and DRA72x_SR1.0 (ABC package)
• TDA2Ex-23 (SR2.0 / ABC package)
• TDA2Px_ABZ_SR1.0_beta
• IODelays for beta devices not guaranteed

DRA78x, TDA3x, and DM50x Beta

• VIN port was updated to split Port A and Port B to be muxed independently (warning: backwards compatibility will break)

PinMux Version 4.0.1512 - Mar 14, 2018

Processors

Newly added devices

• 66AK2G12
• DRA75x / DRA74x (SR2.0 / ABC package)
• DRA71x / DRA79x (SR2.x / CBD package)
• TDA2Ex-17 (SR2.x / CBD package)
• TDA2x (SR2.0 / ABC and AAS packages)
• IODelays for “beta” devices not guaranteed final

AM571x SR2.0 and AM570x SR2.x

• Added support for additional pins that can carry EDC Latch / Sync signals using PRU internal muxing (see “PRU-ICSS Environment” section of AM571x / AM570x TRM)

MSP432E

• The MSP432E QFP package had an incorrect pin-out. This has been fixed (PMUX-1020).

PinMux Version 4.0.1511 - Jan 15, 2018

• Add MSP432P4111 support. No other changes.

PinMux Version 4.0.1510 - Nov 1, 2017

• Add MSP432E support.

PinMux Version 4.0.1508 (Cloud only) - Oct 17, 2017

• Same application as 4.0.1505 below, but infrastructure changes to enable deployment to dev.ti.com.

PinMux Version 4.0.1505 (desktop only) - Oct 16, 2017

• Bug fix: Tool will not load projects created within a window of certain previous tool versions. Projects created before and after this window were OK.

Processors

Newly added devices

• AM570x SR2.0 beta tag dropped
• AM570x SR2.1 now supported
• AM570x renamed to AM570x SR2.x

66AK2Gxx

• fixed code generation output exporting PRU virtual mux modes instead of actual mux mode

PinMux Version 4.0.1496 - July 27, 2017

• Bug fix: 66AKG201 replace USB0 with USB1

PinMux Version 4.0.1495 - July 21, 2017

• Bug fix: PMUX-662 Setting I2C Master on MSP432P01R causes an error

PinMux Version 4.0.1492 - July 6, 2017

• Bug fix: PMUX-654 PinMux comes up blank for TM4C129x

PinMux Version 4.0.1491 - June 28, 2017

Processors

Newly added devices

• AM438x
• AM572x SR1.1 restored (for AM572x and BeagleBoard-X15 early adopters, no known issues but beta tag to remain indefinitely)

AM572x SR2.0 and SR1.1

• Simplified the GPMC timing modes: no longer “1 load” / “5 load” we just have “Default” and “Alternate”

Known Issues

• no new issues to report

PinMux Version 4.0.1490 - May 25, 2017

Processors

Newly added devices

• 66AK2G02
• 66AK2G01

66AK2Gxx

• PMT for Galileo K2G0x based devices is production ready
• New support for 66AK2G01 (K2G02 without DSS, PCIE, PRUSS, and USB1 - incorrect)

Known Issues

• On K2G01 only the USB1 peripheral is available but the PinMux Tool is configured to only allow USB0. Fixed in v4.0.1496.
• K2Gxx PRU - when peripherals from the PRU sub-system are used the tool may export mux modes corresponding to virtual mux mode settings. If the exported mux mode is 6 through 9, then the actual mux mode should be 0. If the exported mux mode is 10-13 (or 0xA through 0xD), the actual mux mode should 1. Fixed in v4.0.1505.

PinMux Version 4.0.1485 - April 25, 2017

Processors

Newly added devices

• AMIC11x
• TDA2PSx beta
• DRA77xP beta

66AK2G0x

• renamed RSV pins to align with the datasheet
• reduced the number of voltage conflict warnings raised

AM335x

• Added U16 as an option for MMC2_DAT7
• aligned GPMC use cases to match TRM Table 7-5 (removed XIP use cases)
• removed “gpevm” from exported file names

AM437x

• added I2C1 to pins N20/T23
• added UART5 to pins A19/B19
• removed “gpevm” from exported file names

All AM57xx

• VIN peripheral is now split into individual Port A and Port B instances
  • this provides more IOSET options and flexibility

AM571x SR2.0

• PRUSS1_MII IOSET3/4 merged together again - allows for 6-Port Ethernet config as seen in the AM5718 IDK board

Known Issues

• All AM57xx: PCIe use case has no function, you still need to modify the CTRL_CORE_PCIE_CONTROL register.
• All AM57xx: VIN peripheral had Port A and Port B split. Older pinmux files will need to recapture VIN.

PinMux Version 4.0.1484 - April 21, 2017

Newly added devices

• mmWave AR14xx, AR16xx

PinMux Version 4.0.1483 - March 8, 2017

Processors

Newly added devices (beta status)

• AM570x
• DM50x
• TDA3x
• DRA78x

66AK2G0x

• Some peripherals were renamed (e.g. eCAP0 is now eCAP_0) - just reselect the peripheral instance to clear the warning
• Added two templates: devicetree.txt and mux-k2g.h for use in Linux and u-boot, respectively
• removed “RX enable” checkbox for all pins (not supported in any BOOTCFG_PADCONFIGx register)
• added “Buffer Class” to pins that support it (i.e. most pins with a BOOTCFG_PADCONFIGx register)
• added warning message whem both PRU MII pins and PRU GPI/O pins are selected (not a supported use case)

AM572x SR2.0

• added template: devicetree.txt for use in Linux (only exports MMC modes for runtime configurations)

AM571x SR2.0

• fixed an issue where the VIP Manual Modes were not applied to the correct VIP IOSETs
• corrected the generated register value for CTRL_CORE_VIP_MUX_SELECT and CTRL_CORE_ALT_SELECT_MUX
  • refer to Table 18-6 of the AM571x and AM570x Technical Reference Manual for details on the above registers
• corrected the generated register value for PRUSSx_GPCFGx (PRU Internal Mux)
  • refer to section 30.2.1 of the AM571x and AM570x Technical Reference Manual for details on the PRU-ICSS Internal Wrapper Multiplexing
• regression: PRUSS1 MII IOSET3 and IOSET4 were unmerged - will raise an IOSET conflict error when using MII0 and MII1 together

Known Issues

• Voltage Conflict Warnings: these are not errors but just notifications to the system designer. The system designer must be aware of the voltage tolerances a pin supports.
  • on 66AK2G the VBUS detect pin is 5.25V tolerable while the USB RTUNE pin should be tied to ground with a resistor, as such it is set to 0.0 V tolerable.
• some peripherals in 66AK2G were renamed causing incompatibility when opening previously saved pinmux files - reselect the peripheral instance to clear the warning
• AM571x SR2.0: the PMT prevents using PRUSS1 IOSET3 and IOSET4 together however this should be a supported use case (see the AM571x Industrial EVM)
• all AM57xx: the VIP module is a unique case where Port A and Port B can be used on two different IOSETs however the PMT disallows this due to IOSET conflict
  • VIP Port A and Port B potentially need to be split and considered separate peripherals in the PMT

Pinmux Version 4.0.1482 - Feb 6, 2017

Processors

AM572x SR2.0

• BETA tag dropped thanks to the below fixes
• MCASP use cases re-written to align with the datasheet
  • Asynchronous or Synchronous mode must be selected as well as the clock signal direction in order for the PinMux Tool to determine the proper timing modes to generate
• fixes in the RTOS output generators where some MMC manual modes weren’t appearing

AM571x SR2.0

• MCASP virtual modes and use cases re-written to align with the datasheet
  • Asynchronous or Synchronous mode must be selected as well as the clock signal direction in order for the PinMux Tool to determine the proper timing modes to generate
• partial fix where VIP Manual Modes are not applied to the correct VIP IOSETs
  • VIN1A IOSET5 / IOSET6 and VIN1B IOSET4 / IOSET5 are still not getting their manual modes applied
• prevented VIP Manual Modes from overlapping when adding multiple VIN instances
• added DSS_VIRTUAL1 to VOUT1 and VOUT3
• merged PRUSS1 MII IOSET3 and IOSET4
• implemented solution to prevent PRUSS2_PRU0 GPI/O pins to be used when PRUSS1_MII0 is used from IOSET3
• using PRUSS1_PRU, PRUSS2_PRU0, and PRUSS2_PRU1 is also prevented when PRUSS1_MII1 is used from IOSET3
• fixes in the RTOS output generators where some MMC manual modes weren’t appearing
• fixed a typo where a MMC4_DS_HS_SDR12_SDR25 mode was exporting labeled as MMC3_DS_HS_SDR12_SDR25
• update GPMC mode names to “Default” and “Alternate” instead of “1 load” and “5 load”
• updated RTOS output generators to preselect peripheral options based on UI selection

Known Issues

• AM571x SR2.0: VIN1A IOSET5 / IOSET6 and VIN1B IOSET4 / IOSET5 are not getting their manual modes applied
• CTRL_CORE_VIP_MUX_SELECT and CTRL_CORE_ALT_SELECT_MUX are not getting the correct register value calculated

Pinmux Version 4.0.1479 - Dec 19, 2016

Processors

66AK2G02

• removed macros for PIN_INPUT and PIN_OUTPUT in the RTOS output (RX enable is not supported in any BOOTCFG_PADCONFIGx register)

All AM57xx

• added SLOW SLEW configurable to VOUT pins (helps reduce power/ground noise and EMI emissions, optional on AM572x and required on AM571x)
• forced RX enable on MMC pins
• removed “Default” mode from MMC1/2 and made “Pad Loopback” the default mode for MMC3/4
• stopped generated code for pins without a CTRL_CORE_PAD_x register

AM572x

• GPIO use cases updated to clearly identify some pins that are INPUT ONLY
• removed MMC4 8-bit use case (MMC4 is 4-bits max)
• made VIN4A IOSET4 export the same Manual Mode as IOSET1

AM571x

• the “GPIO1-5” use case is now five separate “GPIOx” use cases
• removed MMC4 8-bit use case (MMC4 is 4-bits max)
• added PRUSS1 PRU1 parallel capture
• SR2.0 only: updated manual mode IO delays for VIN, VOUT, MMC1/2/3

Known Issues

• All Sitara: the RX enable option on MMC CMD signal and all SPI signals are not enabled by default
• All AM57xx: discovered a typo where MMC4_DS_HS_SDR12_SDR25 mode was exporting as MMC3_DS_HS_SDR12_SDR25
• All AM57xx: MCASP virtual modes not being applied according to datasheet requirements
• All AM57xx: VIP Manual Modes might overlap in RTOS files if multiple VIN instances are used
• All AM57xx: VIP Port A and Port B should be allowed to operate on independent IOSETs
  • the PMT considers Port A + Port B to be one peripheral and therefore mixing IOSETs is not allowed
• All AM57xx: MMC3 and MMC4 had their default options renamed, it’s best to remove and re-add these instances
• All AM57xx: slow slew is not enabled by default on the pins that require it (refer to the RESET values of the CTRL_CORE_PAD_x registers in the AM57xx TRM)
• AM571x SR2.0: VIP_MANUAL modes 4, 6, 7, 8, 10, 11, 12, and 13 are not getting applied