<
#Test setup
[[+y Expand for details about the Test Setup
The base host PC used specification is:
- <font color="#0000f0">Core i7-6820HQ (Quad core, HT enabled, 2,70GHz)</font>
- <font color="#0000f0">16GB 2133MHz DDR4 Non-ECC SDRAM</font>
- <font color="#0000f0">Samsung SSD 512GB M.2 PCIe NVMe Class 40</font>
- <font color="#0000f0">Windows 10 Professional 64 bits</font>
Software components:
- Code Composer Studio <font color="#0000f0">7.2.0.00013</font>
- BlackHawk emupack <font color="#0000f0">6.0.83.003</font>
- Spectrum Digital <font color="#0000f0">emupack 5.2.0.14</font>
- TI Emulators <font color="#0000f0">6.0.628.3</font>
- Segger Jlink SW <font color="#0000f0">6.14e</font>
- Segger Jlink CCS support <font color="#0000f0">6.16.7.0</font>
- BH560v2 firmware rev <font color="#0000f0">5.0.573.0</font>
- ICDI firmware revision <font color="#0000f0">12630</font>
- XDS200 firmware rev <font color="#0000f0">1.0.0.8</font>
- XDS110 firmware rev <font color="#0000f0">2.3.0.8</font>
- MSP432 device support <font color="#0000f0">7.2.4</font>
- C2000 Emulation Flash <font color="#0000f0">1.0.0.5</font>
- C2000 Device support <font color="#0000f0">4.2.0.0</font>
- C6000 device support <font color="#0000f0">1.1.3</font>
- Sitara device support <font color="#0000f0">1.3.5</font>
- TI Tiva/Stellaris device support <font color="#0000f0">2.1.1.15071</font>
<b>Notes:</b>
All JTAG TCLK speeds are 10.368MHz except where noted
All Debug probes are operating in JTAG mode except where noted
+]]
##Important note about JTAG TCLK frequencies:
[[+y Expand for details about TCLK
Some of the emulators allow setting limits to the JTAG TCLK frequency from the CCS Target Configuration editor, which can potentially increase the debugging and loading speed.
However, at the moment of connection the emulator performs some tests on the JTAG serial connection and automatically chooses a reliable TCLK speed, which can be lower than the setting configured in CCS. The most obvious practical effect is that some of the tests below show the same throughput even when setting different TCLK speeds.
For details on the JTAG emulator and board design constraints that affect performance, check the [XDS Target Connection Guide](https://processors.wiki.ti.com/index.php/XDS_Target_Connection_Guide#Target_Connection_Design).
The XDS560 emulators actually report back the reliability of the JTAG TCLK measurements when the <I>Test Connection</I> button is used from the CCS Target Connection editor, and it is shown as:
<pre>
The IR/DR scan-path tests used 50.00MHz as the final frequency.
-----[Measure the source and frequency of the final JTAG TCLKR input]--------
The frequency of the JTAG TCLKR input is measured as 49.99MHz.
</pre>
This helps to know the actual speed being used by the JTAG debugger.
+]]
#Throughput tests
The tests on this section focus on data throughput from the host PC to the target processor to compare the performance of different emulators and JTAG settings.
<b>Note:</b> For MCUs the executable is loaded/executed in Flash and the binaries to SRAM, while for EPs the external RAM is used in all tests.
##Executable Load
The Executable Load throughput test performs a standard program load of an ELF executable to the target device's program memory. The program contains a large data array whose size varies depending on the device's amount of available memory.
###Load results on Cortex M4
Target device: TM4C129NCPDT (TM4C129 connected Launchpad)
<figure>
<figcaption>Executable (.out) load to Flash (kB/s)</figcaption>
</figure>
Target device: MSP432P401 (MSP432 Launchpad Red)
<figure>
<figcaption>Executable (.out) load to Flash (kB/s)</figcaption>
</figure>
###Load results on Cortex A15
Target device: AM5728 (AM5728 IDK)
<figure>
<figcaption>Executable (.out) load to DDR (kB/s)</figcaption>
</figure>
###Load results on Cortex A8
Target device: AM3359 (BeagleBone Rev A4 with TI 20-pin connector)
<figure>
<figcaption>Executable (.out) load to DDR (kB/s)</figcaption>
</figure>
###Load results on C6600
Target device: C6678 (C6678 EVM)
<figure>
<figcaption>Executable (.out) load to DDR (kB/s)</figcaption>
</figure>
###Load results on C6740
Target device: C6748 (C6748 Experimenter's Kit)
<figure>
<figcaption>Executable (.out) load to DDR (kB/s)</figcaption>
</figure>
###Load results on F2800
Target device: TMS320F28377D (TMS320F28377D controlCARD)
<figure>
<figcaption>Executable (.out) load to Flash (kB/s)</figcaption>
</figure>
Target device: TMS320F28335 (TMS320F28335 controlCARD)
<figure>
<figcaption>Executable (.out) load to Flash (kB/s)</figcaption>
</figure>
##Binary Load/Save
The Binary Load/Save throughput tests perform a direct memory load/save to the target device's RAM memory. The binaries are created using the tiobj2bin utility applied to the executables of the previous test, and thus their sizes vary accordingly.
<b>Note:</b> results in <font color="#ff0000">red</font> seem to have been skewed by cache mechanisms.
###Bin results on Cortex M4
Target device: TM4C129NCPDT (TM4C129 connected Launchpad)
<figure>
<figcaption>Binary (.bin) load to SRAM (kB/s) - results in <font color="#ff0000">red</font> seem to have been skewed by cache mechanisms</figcaption>
</figure>
<figure>
<figcaption>Binary (.bin) save from SRAM (kB/s)</figcaption>
</figure>
Target device: MSP432P401 (MSP432 Launchpad Red)
<figure>
<figcaption>Binary (.bin) load to SRAM (kB/s) - results in <font color="#ff0000">red</font> seem to have been skewed by cache mechanisms</figcaption>
</figure>
<figure>
<figcaption>Binary (.bin) save from SRAM (kB/s)</figcaption>
</figure>
###Bin results on Cortex A15
Target device: AM5728 (AM5728 IDK)
<figure>
<figcaption>Binary (.bin) load to DDR (kB/s)</figcaption>
</figure>
<figure>
<figcaption>Binary (.bin) save from DDR (kB/s)</figcaption>
</figure>
###Bin results on Cortex A8
Target device: AM3359 (BeagleBone Rev A4 with TI 20-pin connector)
<figure>
<figcaption>Binary (.bin) load to DDR (kB/s)</figcaption>
</figure>
<figure>
<figcaption>Binary (.bin) save from DDR (kB/s)</figcaption>
</figure>
###Bin results on C6600
Target device: C6678 (C6678 EVM)
<figure>
<figcaption>Binary (.bin) load to DDR (kB/s)</figcaption>
</figure>
<figure>
<figcaption>Binary (.bin) save from DDR (kB/s)</figcaption>
</figure>
###Bin results on C6740
Target device: C6748 (C6748 Experimenter's Kit)
<figure>
<figcaption>Binary (.bin) load to DDR (kB/s)</figcaption>
</figure>
<figure>
<figcaption>Binary (.bin) save from DDR (kB/s)</figcaption>
</figure>
###Bin results on F2800
Target device: TMS320F28377D (TMS320F28377D controlCARD)
<figure>
<figcaption>Binary (.bin) load to SRAM (kB/s) - results in <font color="#ff0000">red</font> seem to have been skewed by cache mechanisms</figcaption>
</figure>
<figure>
<figcaption>Binary (.bin) save from SRAM (kB/s)</figcaption>
</figure>
Target device: TMS320F28335 (TMS320F28335 controlCARD)
<figure>
<figcaption>Binary (.bin) load to SRAM (kB/s)</figcaption>
</figure>
<figure>
<figcaption>Binary (.bin) save from SRAM (kB/s)</figcaption>
</figure>
#Interactive tests
##Console I/O comparison
This test performs a sequence of printf() calls triggered by a well-known recursive program called Towers of Hanoi with 9 disks, which yields 511 console messages printed in sequence of movements.
<b>Note:</b> this test is useful to compare debug probes, as the actual elapsed time is dependent on the RTS implementation and the device itself.
###CIO results on Cortex M4
Target device: TM4C129NCPDT (TM4C129 connected Launchpad)
<figure>
<figcaption>Console I/O output (ms/char)</figcaption>
</figure>
Target device: MSP432P401 (MSP432 Launchpad Red)
<figure>
<figcaption>Console I/O output (ms/char)</figcaption>
</figure>
###CIO results on Cortex A15
Target device: AM5728 (AM5728 IDK)
<figure>
<figcaption>Console I/O output (ms/char)</figcaption>
</figure>
###CIO results on Cortex A8
Target device: AM3359 (BeagleBone White Rev A4 with TI 20-pin connector)
<figure>
<figcaption>Console I/O output (ms/char)</figcaption>
</figure>
###CIO results on C6600
Target device: C6678 (C6678 EVM)
<figure>
<figcaption>Console I/O output (ms/char)</figcaption>
</figure>
###CIO results on C6740
Target device: C6748 (C6748 Experimenter's Kit)
<figure>
<figcaption>Console I/O output (ms/char)</figcaption>
</figure>
###CIO results on F2800
Target device: TMS320F28377D (TMS320F28377D controlCARD)
<figure>
<figcaption>Console I/O output (ms/char)</figcaption>
</figure>
Target device: TMS320F28335 (TMS320F28335 controlCARD)
<figure>
<figcaption>Console I/O output (ms/char)</figcaption>
</figure>
##Step comparison
The single step interactive test performs 500 <I>assembly step into</I> operations using a valid program loaded to the target device's program memory.
###Step results on Cortex M4
Target device: TM4C129NCPDT (TM4C129 connected Launchpad)
<figure>
<figcaption>Single step operations (ms/step)</figcaption>
</figure>
Target device: MSP432P401 (MSP432 Launchpad Red)
<figure>
<figcaption>Single step operations (ms/step)</figcaption>
</figure>
###Step results on Cortex A15
Target device: AM5728 IDK
<figure>
<figcaption>Single step operations (ms/step)</figcaption>
</figure>
###Step results on Cortex A8
Target device: AM3359 (BeagleBone Rev A4 with TI 20-pin connector)
<figure>
<figcaption>Single step operations (ms/step)</figcaption>
</figure>
###Step results on C6600
Target device: C6678 (C6678 EVM)
<figure>
<figcaption>Single step operations (ms/step)</figcaption>
</figure>
###Step results on C6740
Target device: C6748 (C6748 Experimenter's Kit)
<figure>
<figcaption>Single step operations (ms/step)</figcaption>
</figure>
###Step results on F2800
Target device: TMS320F28377D (TMS320F28377D controlCARD)
<figure>
<figcaption>Single step operations (ms/step)</figcaption>
</figure>
Target device: TMS320F28335 (TMS320F28335 controlCARD)
<figure>
<figcaption>Single step operations (ms/step)</figcaption>
</figure>
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